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@@ -31,6 +31,9 @@
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#define DRV_NAME "mpc-i2c"
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+#define MPC_I2C_CLOCK_LEGACY 0
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+#define MPC_I2C_CLOCK_PRESERVE (~0U)
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+
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#define MPC_I2C_FDR 0x04
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#define MPC_I2C_CR 0x08
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#define MPC_I2C_SR 0x0c
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@@ -163,7 +166,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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return 0;
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}
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-#ifdef CONFIG_PPC_MPC52xx
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+#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
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static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
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{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
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{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
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@@ -193,7 +196,7 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
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u32 divider;
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int i;
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- if (!clock)
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+ if (clock == MPC_I2C_CLOCK_LEGACY)
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return -EINVAL;
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/* Determine divider value */
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@@ -221,6 +224,12 @@ static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
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{
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int ret, fdr;
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+ if (clock == MPC_I2C_CLOCK_PRESERVE) {
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+ dev_dbg(i2c->dev, "using fdr %d\n",
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+ readb(i2c->base + MPC_I2C_FDR));
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+ return;
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+ }
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+
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ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
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fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
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@@ -229,13 +238,49 @@ static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
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if (ret >= 0)
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dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
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}
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-#else /* !CONFIG_PPC_MPC52xx */
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+#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
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static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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}
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-#endif /* CONFIG_PPC_MPC52xx*/
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+#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
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+
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+#ifdef CONFIG_PPC_MPC512x
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+static void __devinit mpc_i2c_setup_512x(struct device_node *node,
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+ struct mpc_i2c *i2c,
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+ u32 clock, u32 prescaler)
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+{
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+ struct device_node *node_ctrl;
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+ void __iomem *ctrl;
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+ const u32 *pval;
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+ u32 idx;
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+
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+ /* Enable I2C interrupts for mpc5121 */
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+ node_ctrl = of_find_compatible_node(NULL, NULL,
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+ "fsl,mpc5121-i2c-ctrl");
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+ if (node_ctrl) {
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+ ctrl = of_iomap(node_ctrl, 0);
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+ if (ctrl) {
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+ /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
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+ pval = of_get_property(node, "reg", NULL);
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+ idx = (*pval & 0xff) / 0x20;
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+ setbits32(ctrl, 1 << (24 + idx * 2));
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+ iounmap(ctrl);
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+ }
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+ of_node_put(node_ctrl);
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+ }
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+
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+ /* The clock setup for the 52xx works also fine for the 512x */
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+ mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
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+}
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+#else /* CONFIG_PPC_MPC512x */
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+static void __devinit mpc_i2c_setup_512x(struct device_node *node,
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+ struct mpc_i2c *i2c,
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+ u32 clock, u32 prescaler)
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+{
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+}
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+#endif /* CONFIG_PPC_MPC512x */
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#ifdef CONFIG_FSL_SOC
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static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
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@@ -294,7 +339,7 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
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u32 divider;
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int i;
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- if (!clock)
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+ if (clock == MPC_I2C_CLOCK_LEGACY)
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return -EINVAL;
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/* Determine proper divider value */
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@@ -327,6 +372,13 @@ static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
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{
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int ret, fdr;
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+ if (clock == MPC_I2C_CLOCK_PRESERVE) {
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+ dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
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+ readb(i2c->base + MPC_I2C_DFSRR),
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+ readb(i2c->base + MPC_I2C_FDR));
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+ return;
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+ }
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+
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ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
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fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
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@@ -495,7 +547,7 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
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{
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struct mpc_i2c *i2c;
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const u32 *prop;
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- u32 clock = 0;
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+ u32 clock = MPC_I2C_CLOCK_LEGACY;
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int result = 0;
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int plen;
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@@ -524,20 +576,21 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
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}
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}
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- if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
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+ if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
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+ clock = MPC_I2C_CLOCK_PRESERVE;
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+ } else {
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prop = of_get_property(op->node, "clock-frequency", &plen);
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if (prop && plen == sizeof(u32))
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clock = *prop;
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+ }
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- if (match->data) {
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- struct mpc_i2c_data *data =
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- (struct mpc_i2c_data *)match->data;
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- data->setup(op->node, i2c, clock, data->prescaler);
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- } else {
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- /* Backwards compatibility */
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- if (of_get_property(op->node, "dfsrr", NULL))
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- mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
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- }
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+ if (match->data) {
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+ struct mpc_i2c_data *data = match->data;
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+ data->setup(op->node, i2c, clock, data->prescaler);
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+ } else {
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+ /* Backwards compatibility */
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+ if (of_get_property(op->node, "dfsrr", NULL))
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+ mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
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}
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dev_set_drvdata(&op->dev, i2c);
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@@ -582,6 +635,10 @@ static int __devexit fsl_i2c_remove(struct of_device *op)
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return 0;
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};
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+static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
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+ .setup = mpc_i2c_setup_512x,
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+};
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+
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static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
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.setup = mpc_i2c_setup_52xx,
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};
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@@ -604,6 +661,7 @@ static const struct of_device_id mpc_i2c_of_match[] = {
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{.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
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{.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
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{.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
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+ {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
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{.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
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{.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
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{.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
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@@ -613,7 +671,6 @@ static const struct of_device_id mpc_i2c_of_match[] = {
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};
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MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
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-
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/* Structure for a device driver */
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static struct of_platform_driver mpc_i2c_driver = {
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.match_table = mpc_i2c_of_match,
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@@ -646,5 +703,5 @@ module_exit(fsl_i2c_exit);
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MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
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MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
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- "MPC824x/85xx/52xx processors");
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+ "MPC824x/83xx/85xx/86xx/512x/52xx processors");
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MODULE_LICENSE("GPL");
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