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@@ -1,21 +1,566 @@
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+/*
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+ * Nomadik clock implementation
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+ * Copyright (C) 2013 ST-Ericsson AB
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+ * License terms: GNU General Public License (GPL) version 2
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+ * Author: Linus Walleij <linus.walleij@linaro.org>
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+ */
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+
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+#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
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+
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+#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/debugfs.h>
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+#include <linux/seq_file.h>
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+#include <linux/spinlock.h>
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+#include <linux/reboot.h>
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/*
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* The Nomadik clock tree is described in the STN8815A12 DB V4.2
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* reference manual for the chip, page 94 ff.
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+ * Clock IDs are in the STn8815 Reference Manual table 3, page 27.
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+ */
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+
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+#define SRC_CR 0x00U
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+#define SRC_XTALCR 0x0CU
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+#define SRC_XTALCR_XTALTIMEN BIT(20)
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+#define SRC_XTALCR_SXTALDIS BIT(19)
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+#define SRC_XTALCR_MXTALSTAT BIT(2)
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+#define SRC_XTALCR_MXTALEN BIT(1)
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+#define SRC_XTALCR_MXTALOVER BIT(0)
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+#define SRC_PLLCR 0x10U
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+#define SRC_PLLCR_PLLTIMEN BIT(29)
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+#define SRC_PLLCR_PLL2EN BIT(28)
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+#define SRC_PLLCR_PLL1STAT BIT(2)
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+#define SRC_PLLCR_PLL1EN BIT(1)
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+#define SRC_PLLCR_PLL1OVER BIT(0)
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+#define SRC_PLLFR 0x14U
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+#define SRC_PCKEN0 0x24U
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+#define SRC_PCKDIS0 0x28U
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+#define SRC_PCKENSR0 0x2CU
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+#define SRC_PCKSR0 0x30U
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+#define SRC_PCKEN1 0x34U
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+#define SRC_PCKDIS1 0x38U
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+#define SRC_PCKENSR1 0x3CU
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+#define SRC_PCKSR1 0x40U
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+
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+/* Lock protecting the SRC_CR register */
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+static DEFINE_SPINLOCK(src_lock);
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+/* Base address of the SRC */
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+static void __iomem *src_base;
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+
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+/**
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+ * struct clk_pll1 - Nomadik PLL1 clock
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+ * @hw: corresponding clock hardware entry
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+ * @id: PLL instance: 1 or 2
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+ */
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+struct clk_pll {
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+ struct clk_hw hw;
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+ int id;
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+};
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+
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+/**
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+ * struct clk_src - Nomadik src clock
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+ * @hw: corresponding clock hardware entry
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+ * @id: the clock ID
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+ * @group1: true if the clock is in group1, else it is in group0
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+ * @clkbit: bit 0...31 corresponding to the clock in each clock register
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+ */
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+struct clk_src {
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+ struct clk_hw hw;
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+ int id;
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+ bool group1;
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+ u32 clkbit;
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+};
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+
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+#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
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+#define to_src(_hw) container_of(_hw, struct clk_src, hw)
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+
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+static int pll_clk_enable(struct clk_hw *hw)
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+{
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+ struct clk_pll *pll = to_pll(hw);
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+ u32 val;
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+
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+ spin_lock(&src_lock);
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+ val = readl(src_base + SRC_PLLCR);
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+ if (pll->id == 1) {
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+ if (val & SRC_PLLCR_PLL1OVER) {
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+ val |= SRC_PLLCR_PLL1EN;
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+ writel(val, src_base + SRC_PLLCR);
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+ }
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+ } else if (pll->id == 2) {
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+ val |= SRC_PLLCR_PLL2EN;
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+ writel(val, src_base + SRC_PLLCR);
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+ }
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+ spin_unlock(&src_lock);
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+ return 0;
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+}
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+
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+static void pll_clk_disable(struct clk_hw *hw)
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+{
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+ struct clk_pll *pll = to_pll(hw);
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+ u32 val;
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+
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+ spin_lock(&src_lock);
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+ val = readl(src_base + SRC_PLLCR);
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+ if (pll->id == 1) {
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+ if (val & SRC_PLLCR_PLL1OVER) {
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+ val &= ~SRC_PLLCR_PLL1EN;
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+ writel(val, src_base + SRC_PLLCR);
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+ }
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+ } else if (pll->id == 2) {
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+ val &= ~SRC_PLLCR_PLL2EN;
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+ writel(val, src_base + SRC_PLLCR);
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+ }
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+ spin_unlock(&src_lock);
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+}
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+
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+static int pll_clk_is_enabled(struct clk_hw *hw)
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+{
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+ struct clk_pll *pll = to_pll(hw);
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+ u32 val;
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+
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+ val = readl(src_base + SRC_PLLCR);
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+ if (pll->id == 1) {
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+ if (val & SRC_PLLCR_PLL1OVER)
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+ return !!(val & SRC_PLLCR_PLL1EN);
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+ } else if (pll->id == 2) {
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+ return !!(val & SRC_PLLCR_PLL2EN);
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+ }
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+ return 1;
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+}
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+
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+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct clk_pll *pll = to_pll(hw);
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+ u32 val;
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+
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+ val = readl(src_base + SRC_PLLFR);
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+
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+ if (pll->id == 1) {
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+ u8 mul;
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+ u8 div;
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+
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+ mul = (val >> 8) & 0x3FU;
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+ mul += 2;
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+ div = val & 0x07U;
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+ return (parent_rate * mul) >> div;
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+ }
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+
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+ if (pll->id == 2) {
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+ u8 mul;
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+
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+ mul = (val >> 24) & 0x3FU;
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+ mul += 2;
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+ return (parent_rate * mul);
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+ }
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+
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+ /* Unknown PLL */
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+ return 0;
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+}
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+
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+
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+static const struct clk_ops pll_clk_ops = {
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+ .enable = pll_clk_enable,
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+ .disable = pll_clk_disable,
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+ .is_enabled = pll_clk_is_enabled,
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+ .recalc_rate = pll_clk_recalc_rate,
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+};
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+
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+static struct clk * __init
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+pll_clk_register(struct device *dev, const char *name,
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+ const char *parent_name, u32 id)
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+{
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+ struct clk *clk;
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+ struct clk_pll *pll;
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+ struct clk_init_data init;
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+
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+ if (id != 1 && id != 2) {
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+ pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
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+ return ERR_PTR(-EINVAL);
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+ }
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+
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+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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+ if (!pll) {
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+ pr_err("%s: could not allocate PLL clk\n", __func__);
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+ return ERR_PTR(-ENOMEM);
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+ }
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+
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+ init.name = name;
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+ init.ops = &pll_clk_ops;
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+ init.parent_names = (parent_name ? &parent_name : NULL);
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+ init.num_parents = (parent_name ? 1 : 0);
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+ pll->hw.init = &init;
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+ pll->id = id;
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+
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+ pr_debug("register PLL1 clock \"%s\"\n", name);
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+
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+ clk = clk_register(dev, &pll->hw);
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+ if (IS_ERR(clk))
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+ kfree(pll);
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+
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+ return clk;
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+}
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+
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+/*
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+ * The Nomadik SRC clocks are gated, but not in the sense that
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+ * you read-modify-write a register. Instead there are separate
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+ * clock enable and clock disable registers. Writing a '1' bit in
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+ * the enable register for a certain clock ungates that clock without
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+ * affecting the other clocks. The disable register works the opposite
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+ * way.
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*/
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-static const __initconst struct of_device_id cpu8815_clk_match[] = {
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- { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
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+static int src_clk_enable(struct clk_hw *hw)
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+{
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+ struct clk_src *sclk = to_src(hw);
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+ u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
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+ u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
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+
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+ writel(sclk->clkbit, src_base + enreg);
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+ /* spin until enabled */
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+ while (!(readl(src_base + sreg) & sclk->clkbit))
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+ cpu_relax();
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+ return 0;
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+}
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+
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+static void src_clk_disable(struct clk_hw *hw)
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+{
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+ struct clk_src *sclk = to_src(hw);
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+ u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
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+ u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
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+
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+ writel(sclk->clkbit, src_base + disreg);
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+ /* spin until disabled */
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+ while (readl(src_base + sreg) & sclk->clkbit)
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+ cpu_relax();
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+}
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+
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+static int src_clk_is_enabled(struct clk_hw *hw)
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+{
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+ struct clk_src *sclk = to_src(hw);
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+ u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
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+ u32 val = readl(src_base + sreg);
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+
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+ return !!(val & sclk->clkbit);
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+}
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+
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+static unsigned long
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+src_clk_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ return parent_rate;
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+}
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+
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+static const struct clk_ops src_clk_ops = {
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+ .enable = src_clk_enable,
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+ .disable = src_clk_disable,
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+ .is_enabled = src_clk_is_enabled,
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+ .recalc_rate = src_clk_recalc_rate,
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+};
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+
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+static struct clk * __init
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+src_clk_register(struct device *dev, const char *name,
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+ const char *parent_name, u8 id)
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+{
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+ struct clk *clk;
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+ struct clk_src *sclk;
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+ struct clk_init_data init;
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+
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+ sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
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+ if (!sclk) {
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+ pr_err("could not allocate SRC clock %s\n",
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+ name);
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+ return ERR_PTR(-ENOMEM);
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+ }
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+ init.name = name;
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+ init.ops = &src_clk_ops;
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+ /* Do not force-disable the static SDRAM controller */
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+ if (id == 2)
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+ init.flags = CLK_IGNORE_UNUSED;
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+ else
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+ init.flags = 0;
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+ init.parent_names = (parent_name ? &parent_name : NULL);
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+ init.num_parents = (parent_name ? 1 : 0);
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+ sclk->hw.init = &init;
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+ sclk->id = id;
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+ sclk->group1 = (id > 31);
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+ sclk->clkbit = BIT(id & 0x1f);
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+
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+ pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
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+ name, id, sclk->group1, sclk->clkbit);
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+
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+ clk = clk_register(dev, &sclk->hw);
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+ if (IS_ERR(clk))
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+ kfree(sclk);
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+
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+ return clk;
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+}
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+
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+#ifdef CONFIG_DEBUG_FS
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+
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+static u32 src_pcksr0_boot;
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+static u32 src_pcksr1_boot;
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+
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+static const char * const src_clk_names[] = {
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+ "HCLKDMA0 ",
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+ "HCLKSMC ",
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+ "HCLKSDRAM ",
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+ "HCLKDMA1 ",
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+ "HCLKCLCD ",
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+ "PCLKIRDA ",
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+ "PCLKSSP ",
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+ "PCLKUART0 ",
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+ "PCLKSDI ",
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+ "PCLKI2C0 ",
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+ "PCLKI2C1 ",
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+ "PCLKUART1 ",
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+ "PCLMSP0 ",
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+ "HCLKUSB ",
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+ "HCLKDIF ",
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+ "HCLKSAA ",
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+ "HCLKSVA ",
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+ "PCLKHSI ",
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+ "PCLKXTI ",
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+ "PCLKUART2 ",
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+ "PCLKMSP1 ",
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+ "PCLKMSP2 ",
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+ "PCLKOWM ",
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+ "HCLKHPI ",
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+ "PCLKSKE ",
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+ "PCLKHSEM ",
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+ "HCLK3D ",
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+ "HCLKHASH ",
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+ "HCLKCRYP ",
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+ "PCLKMSHC ",
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+ "HCLKUSBM ",
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+ "HCLKRNG ",
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+ "RESERVED ",
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+ "RESERVED ",
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+ "RESERVED ",
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+ "RESERVED ",
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+ "CLDCLK ",
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+ "IRDACLK ",
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+ "SSPICLK ",
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+ "UART0CLK ",
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+ "SDICLK ",
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+ "I2C0CLK ",
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+ "I2C1CLK ",
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+ "UART1CLK ",
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+ "MSPCLK0 ",
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+ "USBCLK ",
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+ "DIFCLK ",
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+ "IPI2CCLK ",
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+ "IPBMCCLK ",
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+ "HSICLKRX ",
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+ "HSICLKTX ",
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+ "UART2CLK ",
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+ "MSPCLK1 ",
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+ "MSPCLK2 ",
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+ "OWMCLK ",
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+ "RESERVED ",
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+ "SKECLK ",
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+ "RESERVED ",
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+ "3DCLK ",
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+ "PCLKMSP3 ",
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+ "MSPCLK3 ",
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+ "MSHCCLK ",
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+ "USBMCLK ",
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+ "RNGCCLK ",
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+};
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+
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+static int nomadik_src_clk_show(struct seq_file *s, void *what)
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+{
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+ int i;
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+ u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
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+ u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
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+ u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
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+ u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
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+
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+ seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n");
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+ for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
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+ u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
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+ u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
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+ u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
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+ u32 mask = BIT(i & 0x1f);
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+
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+ seq_printf(s, "%s %s %s %s\n",
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+ src_clk_names[i],
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+ (pcksrb & mask) ? "on " : "off",
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+ (pcksr & mask) ? "on " : "off",
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+ (pckreq & mask) ? "on " : "off");
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+ }
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+ return 0;
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+}
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+
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+static int nomadik_src_clk_open(struct inode *inode, struct file *file)
|
|
|
+{
|
|
|
+ return single_open(file, nomadik_src_clk_show, NULL);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct file_operations nomadik_src_clk_debugfs_ops = {
|
|
|
+ .open = nomadik_src_clk_open,
|
|
|
+ .read = seq_read,
|
|
|
+ .llseek = seq_lseek,
|
|
|
+ .release = single_release,
|
|
|
+};
|
|
|
+
|
|
|
+static int __init nomadik_src_clk_init_debugfs(void)
|
|
|
+{
|
|
|
+ src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
|
|
|
+ src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
|
|
|
+ debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
|
|
|
+ NULL, NULL, &nomadik_src_clk_debugfs_ops);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+module_init(nomadik_src_clk_init_debugfs);
|
|
|
+
|
|
|
+#endif
|
|
|
+
|
|
|
+static void __init of_nomadik_pll_setup(struct device_node *np)
|
|
|
+{
|
|
|
+ struct clk *clk = ERR_PTR(-EINVAL);
|
|
|
+ const char *clk_name = np->name;
|
|
|
+ const char *parent_name;
|
|
|
+ u32 pll_id;
|
|
|
+
|
|
|
+ if (of_property_read_u32(np, "pll-id", &pll_id)) {
|
|
|
+ pr_err("%s: PLL \"%s\" missing pll-id property\n",
|
|
|
+ __func__, clk_name);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ parent_name = of_clk_get_parent_name(np, 0);
|
|
|
+ clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
|
|
|
+ if (!IS_ERR(clk))
|
|
|
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
+}
|
|
|
+
|
|
|
+static void __init of_nomadik_hclk_setup(struct device_node *np)
|
|
|
+{
|
|
|
+ struct clk *clk = ERR_PTR(-EINVAL);
|
|
|
+ const char *clk_name = np->name;
|
|
|
+ const char *parent_name;
|
|
|
+
|
|
|
+ parent_name = of_clk_get_parent_name(np, 0);
|
|
|
+ /*
|
|
|
+ * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
|
|
|
+ */
|
|
|
+ clk = clk_register_divider(NULL, clk_name, parent_name,
|
|
|
+ 0, src_base + SRC_CR,
|
|
|
+ 13, 2,
|
|
|
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
|
|
+ &src_lock);
|
|
|
+ if (!IS_ERR(clk))
|
|
|
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
+}
|
|
|
+
|
|
|
+static void __init of_nomadik_src_clk_setup(struct device_node *np)
|
|
|
+{
|
|
|
+ struct clk *clk = ERR_PTR(-EINVAL);
|
|
|
+ const char *clk_name = np->name;
|
|
|
+ const char *parent_name;
|
|
|
+ u32 clk_id;
|
|
|
+
|
|
|
+ if (of_property_read_u32(np, "clock-id", &clk_id)) {
|
|
|
+ pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
|
|
|
+ __func__, clk_name);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ parent_name = of_clk_get_parent_name(np, 0);
|
|
|
+ clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
|
|
|
+ if (!IS_ERR(clk))
|
|
|
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
+}
|
|
|
+
|
|
|
+static const __initconst struct of_device_id nomadik_src_match[] = {
|
|
|
+ { .compatible = "stericsson,nomadik-src" },
|
|
|
{ /* sentinel */ }
|
|
|
};
|
|
|
|
|
|
+static const __initconst struct of_device_id nomadik_src_clk_match[] = {
|
|
|
+ {
|
|
|
+ .compatible = "fixed-clock",
|
|
|
+ .data = of_fixed_clk_setup,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "fixed-factor-clock",
|
|
|
+ .data = of_fixed_factor_clk_setup,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "st,nomadik-pll-clock",
|
|
|
+ .data = of_nomadik_pll_setup,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "st,nomadik-hclk-clock",
|
|
|
+ .data = of_nomadik_hclk_setup,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "st,nomadik-src-clock",
|
|
|
+ .data = of_nomadik_src_clk_setup,
|
|
|
+ },
|
|
|
+ { /* sentinel */ }
|
|
|
+};
|
|
|
+
|
|
|
+static int nomadik_clk_reboot_handler(struct notifier_block *this,
|
|
|
+ unsigned long code,
|
|
|
+ void *unused)
|
|
|
+{
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ /* The main chrystal need to be enabled for reboot to work */
|
|
|
+ val = readl(src_base + SRC_XTALCR);
|
|
|
+ val &= ~SRC_XTALCR_MXTALOVER;
|
|
|
+ val |= SRC_XTALCR_MXTALEN;
|
|
|
+ pr_crit("force-enabling MXTALO\n");
|
|
|
+ writel(val, src_base + SRC_XTALCR);
|
|
|
+ return NOTIFY_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static struct notifier_block nomadik_clk_reboot_notifier = {
|
|
|
+ .notifier_call = nomadik_clk_reboot_handler,
|
|
|
+};
|
|
|
+
|
|
|
void __init nomadik_clk_init(void)
|
|
|
{
|
|
|
- of_clk_init(cpu8815_clk_match);
|
|
|
+ struct device_node *np;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ np = of_find_matching_node(NULL, nomadik_src_match);
|
|
|
+ if (!np) {
|
|
|
+ pr_crit("no matching node for SRC, aborting clock init\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ src_base = of_iomap(np, 0);
|
|
|
+ if (!src_base) {
|
|
|
+ pr_err("%s: must have src parent node with REGS (%s)\n",
|
|
|
+ __func__, np->name);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ val = readl(src_base + SRC_XTALCR);
|
|
|
+ pr_info("SXTALO is %s\n",
|
|
|
+ (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
|
|
|
+ pr_info("MXTAL is %s\n",
|
|
|
+ (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
|
|
|
+ if (of_property_read_bool(np, "disable-sxtalo")) {
|
|
|
+ /* The machine uses an external oscillator circuit */
|
|
|
+ val |= SRC_XTALCR_SXTALDIS;
|
|
|
+ pr_info("disabling SXTALO\n");
|
|
|
+ }
|
|
|
+ if (of_property_read_bool(np, "disable-mxtalo")) {
|
|
|
+ /* Disable this too: also run by external oscillator */
|
|
|
+ val |= SRC_XTALCR_MXTALOVER;
|
|
|
+ val &= ~SRC_XTALCR_MXTALEN;
|
|
|
+ pr_info("disabling MXTALO\n");
|
|
|
+ }
|
|
|
+ writel(val, src_base + SRC_XTALCR);
|
|
|
+ register_reboot_notifier(&nomadik_clk_reboot_notifier);
|
|
|
+
|
|
|
+ of_clk_init(nomadik_src_clk_match);
|
|
|
}
|
Linus Walleij