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@@ -296,21 +296,25 @@ irqreturn_t mxr_irq_handler(int irq, void *dev_data)
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/* wake up process waiting for VSYNC */
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if (val & MXR_INT_STATUS_VSYNC) {
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set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
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+ /* toggle TOP field event if working in interlaced mode */
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+ if (~mxr_read(mdev, MXR_CFG) & MXR_CFG_SCAN_PROGRASSIVE)
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+ change_bit(MXR_EVENT_TOP, &mdev->event_flags);
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wake_up(&mdev->event_queue);
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- }
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-
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- /* clear interrupts */
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- if (~val & MXR_INT_EN_VSYNC) {
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/* vsync interrupt use different bit for read and clear */
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- val &= ~MXR_INT_EN_VSYNC;
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+ val &= ~MXR_INT_STATUS_VSYNC;
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val |= MXR_INT_CLEAR_VSYNC;
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}
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+
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+ /* clear interrupts */
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mxr_write(mdev, MXR_INT_STATUS, val);
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spin_unlock(&mdev->reg_slock);
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/* leave on non-vsync event */
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if (~val & MXR_INT_CLEAR_VSYNC)
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return IRQ_HANDLED;
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+ /* skip layer update on bottom field */
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+ if (!test_bit(MXR_EVENT_TOP, &mdev->event_flags))
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+ return IRQ_HANDLED;
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for (i = 0; i < MXR_MAX_LAYERS; ++i)
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mxr_irq_layer_handle(mdev->layer[i]);
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return IRQ_HANDLED;
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@@ -333,6 +337,7 @@ void mxr_reg_streamon(struct mxr_device *mdev)
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/* start MIXER */
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mxr_write_mask(mdev, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
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+ set_bit(MXR_EVENT_TOP, &mdev->event_flags);
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spin_unlock_irqrestore(&mdev->reg_slock, flags);
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}
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