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@@ -723,17 +723,18 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
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if (is_lvds) {
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u32 lvds = REG_READ(LVDS);
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- lvds |=
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- LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
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- LVDS_PIPEB_SELECT;
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+ lvds &= ~LVDS_PIPEB_SELECT;
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+ if (pipe == 1)
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+ lvds |= LVDS_PIPEB_SELECT;
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+
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+ lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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/* Set the B0-B3 data pairs corresponding to
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* whether we're going to
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* set the DPLLs for dual-channel mode or not.
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*/
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+ lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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if (clock.p2 == 7)
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lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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- else
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- lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
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* appropriately here, but we need to look more
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