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@@ -46,6 +46,9 @@
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* gpio13: cs5345 reset pin
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*/
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+/*
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+ * File scope utility functions
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+ */
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static void gpio_write(struct cx18 *cx)
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{
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u32 dir_lo = cx->gpio_dir & 0xffff;
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@@ -63,73 +66,201 @@ static void gpio_write(struct cx18 *cx)
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CX18_REG_GPIO_OUT2, val_hi, dir_hi);
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}
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-void cx18_reset_i2c_slaves_gpio(struct cx18 *cx)
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+static void gpio_update(struct cx18 *cx, u32 mask, u32 data)
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{
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- const struct cx18_gpio_i2c_slave_reset *p;
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+ if (mask == 0)
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+ return;
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- p = &cx->card->gpio_i2c_slave_reset;
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+ mutex_lock(&cx->gpio_lock);
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+ cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask);
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+ gpio_write(cx);
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+ mutex_unlock(&cx->gpio_lock);
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+}
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+
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+static void gpio_reset_seq(struct cx18 *cx, u32 active_lo, u32 active_hi,
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+ unsigned int assert_msecs,
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+ unsigned int recovery_msecs)
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+{
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+ u32 mask;
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- if ((p->active_lo_mask | p->active_hi_mask) == 0)
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+ mask = active_lo | active_hi;
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+ if (mask == 0)
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return;
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- /* Assuming that the masks are a subset of the bits in gpio_dir */
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+ /*
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+ * Assuming that active_hi and active_lo are a subsets of the bits in
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+ * gpio_dir. Also assumes that active_lo and active_hi don't overlap
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+ * in any bit position
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+ */
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/* Assert */
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- mutex_lock(&cx->gpio_lock);
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- cx->gpio_val =
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- (cx->gpio_val | p->active_hi_mask) & ~(p->active_lo_mask);
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- gpio_write(cx);
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- schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_asserted));
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+ gpio_update(cx, mask, ~active_lo);
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+ schedule_timeout_uninterruptible(msecs_to_jiffies(assert_msecs));
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/* Deassert */
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- cx->gpio_val =
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- (cx->gpio_val | p->active_lo_mask) & ~(p->active_hi_mask);
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- gpio_write(cx);
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- schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_recovery));
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+ gpio_update(cx, mask, ~active_hi);
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+ schedule_timeout_uninterruptible(msecs_to_jiffies(recovery_msecs));
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+}
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+
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+/*
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+ * GPIO Multiplexer - logical device
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+ */
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+static int gpiomux_log_status(struct v4l2_subdev *sd)
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+{
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+ struct cx18 *cx = v4l2_get_subdevdata(sd);
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+
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+ mutex_lock(&cx->gpio_lock);
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+ CX18_INFO("GPIO: direction 0x%08x, value 0x%08x\n",
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+ cx->gpio_dir, cx->gpio_val);
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mutex_unlock(&cx->gpio_lock);
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+ return 0;
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}
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-void cx18_reset_ir_gpio(void *data)
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+static int gpiomux_s_radio(struct v4l2_subdev *sd)
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{
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- struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
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- const struct cx18_gpio_i2c_slave_reset *p;
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+ struct cx18 *cx = v4l2_get_subdevdata(sd);
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- p = &cx->card->gpio_i2c_slave_reset;
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+ /*
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+ * FIXME - work out the cx->active/audio_input mess - this is
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+ * intended to handle the switch to radio mode and set the
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+ * audio routing, but we need to update the state in cx
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+ */
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+ gpio_update(cx, cx->card->gpio_audio_input.mask,
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+ cx->card->gpio_audio_input.radio);
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+ return 0;
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+}
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- if (p->ir_reset_mask == 0)
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- return;
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+static int gpiomux_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
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+{
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+ struct cx18 *cx = v4l2_get_subdevdata(sd);
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+ u32 data;
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- CX18_DEBUG_INFO("Resetting IR microcontroller\n");
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+ switch (cx->card->audio_inputs[cx->audio_input].muxer_input) {
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+ case 1:
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+ data = cx->card->gpio_audio_input.linein;
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+ break;
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+ case 0:
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+ data = cx->card->gpio_audio_input.tuner;
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+ break;
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+ default:
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+ /*
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+ * FIXME - work out the cx->active/audio_input mess - this is
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+ * intended to handle the switch from radio mode and set the
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+ * audio routing, but we need to update the state in cx
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+ */
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+ data = cx->card->gpio_audio_input.tuner;
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+ break;
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+ }
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+ gpio_update(cx, cx->card->gpio_audio_input.mask, data);
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+ return 0;
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+}
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- /*
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- Assert timing for the Z8F0811 on HVR-1600 boards:
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- 1. Assert RESET for min of 4 clock cycles at 18.432 MHz to initiate
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- 2. Reset then takes 66 WDT cycles at 10 kHz + 16 xtal clock cycles
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- (6,601,085 nanoseconds ~= 7 milliseconds)
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- 3. DBG pin must be high before chip exits reset for normal operation.
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- DBG is open drain and hopefully pulled high since we don't
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- normally drive it (GPIO 1?) for the HVR-1600
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- 4. Z8F0811 won't exit reset until RESET is deasserted
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- */
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- mutex_lock(&cx->gpio_lock);
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- cx->gpio_val = cx->gpio_val & ~p->ir_reset_mask;
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- gpio_write(cx);
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- mutex_unlock(&cx->gpio_lock);
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- schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_asserted));
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+static int gpiomux_s_audio_routing(struct v4l2_subdev *sd,
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+ const struct v4l2_routing *route)
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+{
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+ struct cx18 *cx = v4l2_get_subdevdata(sd);
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+ u32 data;
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+
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+ switch (route->input) {
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+ case 0:
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+ data = cx->card->gpio_audio_input.tuner;
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+ break;
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+ case 1:
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+ data = cx->card->gpio_audio_input.linein;
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+ break;
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+ case 2:
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+ data = cx->card->gpio_audio_input.radio;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+ gpio_update(cx, cx->card->gpio_audio_input.mask, data);
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+ return 0;
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+}
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+
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+static const struct v4l2_subdev_core_ops gpiomux_core_ops = {
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+ .log_status = gpiomux_log_status,
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+};
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+
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+static const struct v4l2_subdev_tuner_ops gpiomux_tuner_ops = {
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+ .s_std = gpiomux_s_std,
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+ .s_radio = gpiomux_s_radio,
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+};
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+
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+static const struct v4l2_subdev_audio_ops gpiomux_audio_ops = {
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+ .s_routing = gpiomux_s_audio_routing,
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+};
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+
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+static const struct v4l2_subdev_ops gpiomux_ops = {
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+ .core = &gpiomux_core_ops,
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+ .tuner = &gpiomux_tuner_ops,
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+ .audio = &gpiomux_audio_ops,
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+};
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+
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+/*
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+ * GPIO Reset Controller - logical device
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+ */
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+static int resetctrl_log_status(struct v4l2_subdev *sd)
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+{
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+ struct cx18 *cx = v4l2_get_subdevdata(sd);
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- /*
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- Zilog comes out of reset, loads reset vector address and executes
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- from there. Required recovery delay unknown.
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- */
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mutex_lock(&cx->gpio_lock);
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- cx->gpio_val = cx->gpio_val | p->ir_reset_mask;
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- gpio_write(cx);
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+ CX18_INFO("GPIO: direction 0x%08x, value 0x%08x\n",
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+ cx->gpio_dir, cx->gpio_val);
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mutex_unlock(&cx->gpio_lock);
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- schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_recovery));
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+ return 0;
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}
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-EXPORT_SYMBOL(cx18_reset_ir_gpio);
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-/* This symbol is exported for use by an infrared module for the IR-blaster */
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+static int resetctrl_reset(struct v4l2_subdev *sd, u32 val)
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+{
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+ struct cx18 *cx = v4l2_get_subdevdata(sd);
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+ const struct cx18_gpio_i2c_slave_reset *p;
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+
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+ p = &cx->card->gpio_i2c_slave_reset;
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+ switch (val) {
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+ case CX18_GPIO_RESET_I2C:
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+ gpio_reset_seq(cx, p->active_lo_mask, p->active_hi_mask,
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+ p->msecs_asserted, p->msecs_recovery);
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+ break;
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+ case CX18_GPIO_RESET_Z8F0811:
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+ /*
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+ * Assert timing for the Z8F0811 on HVR-1600 boards:
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+ * 1. Assert RESET for min of 4 clock cycles at 18.432 MHz to
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+ * initiate
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+ * 2. Reset then takes 66 WDT cycles at 10 kHz + 16 xtal clock
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+ * cycles (6,601,085 nanoseconds ~= 7 milliseconds)
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+ * 3. DBG pin must be high before chip exits reset for normal
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+ * operation. DBG is open drain and hopefully pulled high
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+ * since we don't normally drive it (GPIO 1?) for the
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+ * HVR-1600
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+ * 4. Z8F0811 won't exit reset until RESET is deasserted
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+ * 5. Zilog comes out of reset, loads reset vector address and
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+ * executes from there. Required recovery delay unknown.
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+ */
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+ gpio_reset_seq(cx, p->ir_reset_mask, 0,
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+ p->msecs_asserted, p->msecs_recovery);
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+ break;
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+ case CX18_GPIO_RESET_XC2028:
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+ if (cx->card->tuners[0].tuner == TUNER_XC2028)
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+ gpio_reset_seq(cx, (1 << cx->card->xceive_pin), 0,
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+ 1, 1);
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+ break;
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+ }
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+ return 0;
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+}
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+
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+static const struct v4l2_subdev_core_ops resetctrl_core_ops = {
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+ .log_status = resetctrl_log_status,
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+ .reset = resetctrl_reset,
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+};
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+
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+static const struct v4l2_subdev_ops resetctrl_ops = {
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+ .core = &resetctrl_core_ops,
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+};
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+
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+/*
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+ * External entry points
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+ */
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void cx18_gpio_init(struct cx18 *cx)
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{
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mutex_lock(&cx->gpio_lock);
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@@ -156,6 +287,49 @@ void cx18_gpio_init(struct cx18 *cx)
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mutex_unlock(&cx->gpio_lock);
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}
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+int cx18_gpio_register(struct cx18 *cx, u32 hw)
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+{
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+ struct v4l2_subdev *sd;
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+ const struct v4l2_subdev_ops *ops;
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+ char *str;
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+
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+ switch (hw) {
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+ case CX18_HW_GPIO_MUX:
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+ sd = &cx->sd_gpiomux;
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+ ops = &gpiomux_ops;
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+ str = "gpio mux";
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+ break;
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+ case CX18_HW_GPIO_RESET_CTRL:
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+ sd = &cx->sd_resetctrl;
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+ ops = &resetctrl_ops;
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+ str = "gpio reset ctrl";
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ v4l2_subdev_init(sd, ops);
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+ v4l2_set_subdevdata(sd, cx);
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+ snprintf(sd->name, sizeof(sd->name), "%s %s", cx->v4l2_dev.name, str);
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+ sd->grp_id = hw;
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+ return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
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+}
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+
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+void cx18_reset_ir_gpio(void *data)
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+{
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+ struct cx18 *cx = to_cx18((struct v4l2_device *)data);
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+
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+ if (cx->card->gpio_i2c_slave_reset.ir_reset_mask == 0)
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+ return;
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+
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+ CX18_DEBUG_INFO("Resetting IR microcontroller\n");
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+
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+ v4l2_subdev_call(&cx->sd_resetctrl,
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+ core, reset, CX18_GPIO_RESET_Z8F0811);
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+}
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+EXPORT_SYMBOL(cx18_reset_ir_gpio);
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+/* This symbol is exported for use by lirc_pvr150 for the IR-blaster */
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+
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/* Xceive tuner reset function */
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int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value)
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{
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@@ -163,56 +337,11 @@ int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value)
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struct cx18_i2c_algo_callback_data *cb_data = algo->data;
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struct cx18 *cx = cb_data->cx;
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- if (cmd != XC2028_TUNER_RESET)
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+ if (cmd != XC2028_TUNER_RESET ||
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+ cx->card->tuners[0].tuner != TUNER_XC2028)
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return 0;
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- CX18_DEBUG_INFO("Resetting tuner\n");
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- mutex_lock(&cx->gpio_lock);
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- cx->gpio_val &= ~(1 << cx->card->xceive_pin);
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- gpio_write(cx);
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- mutex_unlock(&cx->gpio_lock);
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- schedule_timeout_interruptible(msecs_to_jiffies(1));
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-
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- mutex_lock(&cx->gpio_lock);
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- cx->gpio_val |= 1 << cx->card->xceive_pin;
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- gpio_write(cx);
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- mutex_unlock(&cx->gpio_lock);
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- schedule_timeout_interruptible(msecs_to_jiffies(1));
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- return 0;
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-}
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-
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-int cx18_gpio(struct cx18 *cx, unsigned int command, void *arg)
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-{
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- struct v4l2_routing *route = arg;
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- u32 mask, data;
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-
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- switch (command) {
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- case VIDIOC_INT_S_AUDIO_ROUTING:
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- if (route->input > 2)
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- return -EINVAL;
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- mask = cx->card->gpio_audio_input.mask;
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- switch (route->input) {
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- case 0:
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- data = cx->card->gpio_audio_input.tuner;
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- break;
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- case 1:
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- data = cx->card->gpio_audio_input.linein;
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- break;
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- case 2:
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- default:
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- data = cx->card->gpio_audio_input.radio;
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- break;
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- }
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- break;
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-
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- default:
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- return -EINVAL;
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- }
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- if (mask) {
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- mutex_lock(&cx->gpio_lock);
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- cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask);
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- gpio_write(cx);
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- mutex_unlock(&cx->gpio_lock);
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- }
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- return 0;
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+ CX18_DEBUG_INFO("Resetting XCeive tuner\n");
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+ return v4l2_subdev_call(&cx->sd_resetctrl,
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+ core, reset, CX18_GPIO_RESET_XC2028);
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}
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Andy Walls