|
@@ -20,6 +20,7 @@
|
|
|
#define _EFER_LMA 10 /* Long mode active (read-only) */
|
|
|
#define _EFER_NX 11 /* No execute enable */
|
|
|
#define _EFER_SVME 12 /* Enable virtualization */
|
|
|
+#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
|
|
|
#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
|
|
|
|
|
|
#define EFER_SCE (1<<_EFER_SCE)
|
|
@@ -27,6 +28,7 @@
|
|
|
#define EFER_LMA (1<<_EFER_LMA)
|
|
|
#define EFER_NX (1<<_EFER_NX)
|
|
|
#define EFER_SVME (1<<_EFER_SVME)
|
|
|
+#define EFER_LMSLE (1<<_EFER_LMSLE)
|
|
|
#define EFER_FFXSR (1<<_EFER_FFXSR)
|
|
|
|
|
|
/* Intel MSRs. Some also available on other CPUs */
|