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@@ -466,6 +466,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
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clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
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clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
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+ clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc");
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/* set SDHC root clock to 200MHZ*/
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clk_set_rate(clk[esdhc_a_podf], 200000000);
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