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@@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = {
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static void am35xx_enable_emac_int(void)
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{
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- u32 regval;
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-
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- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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- regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
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- AM35XX_CPGMAC_C0_TX_PULSE_CLR |
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- AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
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- AM35XX_CPGMAC_C0_RX_THRESH_CLR);
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- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
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- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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+ u32 v;
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+
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+ v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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+ v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
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+ AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
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+ omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
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+ omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
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}
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static void am35xx_disable_emac_int(void)
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{
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- u32 regval;
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+ u32 v;
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- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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- regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
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- AM35XX_CPGMAC_C0_TX_PULSE_CLR);
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- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
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- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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+ v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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+ v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
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+ omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
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+ omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
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}
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static struct emac_platform_data am35xx_emac_pdata = {
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@@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = {
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void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
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{
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- unsigned int regval;
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+ u32 v;
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int err;
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am35xx_emac_pdata.rmii_en = rmii_en;
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@@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
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return;
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}
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- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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- regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
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- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
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- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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+ v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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+ v &= ~AM35XX_CPGMACSS_SW_RST;
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+ omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
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+ omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
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}
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