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@@ -301,8 +301,9 @@ enum {
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MV_HP_ERRATA_60X1B2 = (1 << 3),
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MV_HP_ERRATA_60X1C0 = (1 << 4),
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MV_HP_ERRATA_XX42A0 = (1 << 5),
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- MV_HP_50XX = (1 << 6),
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- MV_HP_GEN_IIE = (1 << 7),
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+ MV_HP_GEN_I = (1 << 6),
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+ MV_HP_GEN_II = (1 << 7),
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+ MV_HP_GEN_IIE = (1 << 8),
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/* Port private flags (pp_flags) */
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MV_PP_FLAG_EDMA_EN = (1 << 0),
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@@ -310,10 +311,8 @@ enum {
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MV_PP_FLAG_HAD_A_RESET = (1 << 2),
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};
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-#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
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-#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
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-#define IS_GEN_I(hpriv) IS_50XX(hpriv)
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-#define IS_GEN_II(hpriv) IS_60XX(hpriv)
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+#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
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+#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
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#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
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enum {
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@@ -1406,7 +1405,7 @@ static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
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", dev disconnect" : ", dev connect");
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}
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- if (IS_50XX(hpriv)) {
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+ if (IS_GEN_I(hpriv)) {
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eh_freeze_mask = EDMA_EH_FREEZE_5;
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if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
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@@ -2100,7 +2099,7 @@ static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
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writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
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- if (IS_60XX(hpriv)) {
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+ if (IS_GEN_II(hpriv)) {
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u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
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ifctl |= (1 << 7); /* enable gen2i speed */
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ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
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@@ -2116,7 +2115,7 @@ static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
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hpriv->ops->phy_errata(hpriv, mmio, port_no);
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- if (IS_50XX(hpriv))
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+ if (IS_GEN_I(hpriv))
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mdelay(1);
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}
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@@ -2163,7 +2162,7 @@ comreset_retry:
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} while (time_before(jiffies, deadline));
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/* work around errata */
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- if (IS_60XX(hpriv) &&
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+ if (IS_GEN_II(hpriv) &&
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(sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
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(retry-- > 0))
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goto comreset_retry;
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@@ -2396,7 +2395,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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switch(board_idx) {
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case chip_5080:
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hpriv->ops = &mv5xxx_ops;
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- hp_flags |= MV_HP_50XX;
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+ hp_flags |= MV_HP_GEN_I;
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switch (rev_id) {
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case 0x1:
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@@ -2416,7 +2415,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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case chip_504x:
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case chip_508x:
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hpriv->ops = &mv5xxx_ops;
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- hp_flags |= MV_HP_50XX;
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+ hp_flags |= MV_HP_GEN_I;
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switch (rev_id) {
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case 0x0:
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@@ -2436,6 +2435,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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case chip_604x:
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case chip_608x:
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hpriv->ops = &mv6xxx_ops;
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+ hp_flags |= MV_HP_GEN_II;
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switch (rev_id) {
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case 0x7:
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@@ -2455,7 +2455,6 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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case chip_7042:
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case chip_6042:
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hpriv->ops = &mv6xxx_ops;
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-
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hp_flags |= MV_HP_GEN_IIE;
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switch (rev_id) {
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@@ -2522,7 +2521,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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hpriv->ops->enable_leds(hpriv, mmio);
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for (port = 0; port < host->n_ports; port++) {
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- if (IS_60XX(hpriv)) {
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+ if (IS_GEN_II(hpriv)) {
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void __iomem *port_mmio = mv_port_base(mmio, port);
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u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
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@@ -2557,7 +2556,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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/* and unmask interrupt generation for host regs */
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writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
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- if (IS_50XX(hpriv))
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+ if (IS_GEN_I(hpriv))
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writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
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else
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writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
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