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+/*
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+ * arch/arch/mach-ixp4xx/vulcan-pci.c
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+ *
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+ * Vulcan board-level PCI initialization
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+ *
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+ * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
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+ *
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+ * based on ixdp425-pci.c:
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+ * Copyright (C) 2002 Intel Corporation.
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+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/pci.h>
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+#include <linux/init.h>
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+#include <linux/irq.h>
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+#include <asm/mach/pci.h>
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+#include <asm/mach-types.h>
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+
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+/* PCI controller GPIO to IRQ pin mappings */
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+#define INTA 2
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+#define INTB 3
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+
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+void __init vulcan_pci_preinit(void)
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+{
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+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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+ /*
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+ * Cardbus bridge wants way more than the SoC can actually offer,
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+ * and leaves the whole PCI bus in a mess. Artificially limit it
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+ * to 8MB per region. Of course indirect mode doesn't have this
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+ * limitation...
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+ */
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+ pci_cardbus_mem_size = SZ_8M;
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+ pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
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+ (int)(pci_cardbus_mem_size >> 20));
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+#endif
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+ set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
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+ set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
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+ ixp4xx_pci_preinit();
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+}
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+
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+static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ if (slot == 1)
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+ return IXP4XX_GPIO_IRQ(INTA);
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+
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+ if (slot == 2)
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+ return IXP4XX_GPIO_IRQ(INTB);
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+
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+ return -1;
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+}
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+
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+struct hw_pci vulcan_pci __initdata = {
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+ .nr_controllers = 1,
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+ .preinit = vulcan_pci_preinit,
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+ .swizzle = pci_std_swizzle,
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+ .setup = ixp4xx_setup,
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+ .scan = ixp4xx_scan_bus,
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+ .map_irq = vulcan_map_irq,
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+};
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+
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+int __init vulcan_pci_init(void)
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+{
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+ if (machine_is_arcom_vulcan())
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+ pci_common_init(&vulcan_pci);
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+ return 0;
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+}
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+
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+subsys_initcall(vulcan_pci_init);
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