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+/*
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+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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+ */
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+#include <asm/sizes.h>
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+#include <mach/mx23.h>
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+#include <mach/mx28.h>
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+#include <mach/devices-common.h>
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+#include <linux/dma-mapping.h>
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+
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+#ifdef CONFIG_SOC_IMX23
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+const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
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+ .devid = "imx23-gpmi-nand",
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+ .res = {
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+ /* GPMI */
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+ DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
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+ GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
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+ DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
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+ GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
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+ /* BCH */
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+ DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
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+ GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
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+ DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
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+ GPMI_NAND_BCH_INTERRUPT_RES_NAME),
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+ /* DMA */
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+ DEFINE_RES_NAMED(MX23_DMA_GPMI0,
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+ MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
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+ GPMI_NAND_DMA_CHANNELS_RES_NAME,
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+ IORESOURCE_DMA),
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+ DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
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+ GPMI_NAND_DMA_INTERRUPT_RES_NAME),
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+ },
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+};
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+#endif
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+
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+#ifdef CONFIG_SOC_IMX28
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+const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
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+ .devid = "imx28-gpmi-nand",
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+ .res = {
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+ /* GPMI */
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+ DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
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+ GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
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+ DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
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+ GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
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+ /* BCH */
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+ DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
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+ GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
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+ DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
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+ GPMI_NAND_BCH_INTERRUPT_RES_NAME),
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+ /* DMA */
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+ DEFINE_RES_NAMED(MX28_DMA_GPMI0,
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+ MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
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+ GPMI_NAND_DMA_CHANNELS_RES_NAME,
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+ IORESOURCE_DMA),
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+ DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
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+ GPMI_NAND_DMA_INTERRUPT_RES_NAME),
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+ },
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+};
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+#endif
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+
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+struct platform_device *__init
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+mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
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+ const struct mxs_gpmi_nand_data *data)
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+{
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+ return mxs_add_platform_device_dmamask(data->devid, -1,
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+ data->res, GPMI_NAND_RES_SIZE,
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+ pdata, sizeof(*pdata), DMA_BIT_MASK(32));
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+}
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