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@@ -140,6 +140,7 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
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static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
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{
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struct iommu_cmd cmd;
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+ int ret;
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BUG_ON(iommu == NULL);
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@@ -147,9 +148,11 @@ static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
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CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
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cmd.data[0] = devid;
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+ ret = iommu_queue_command(iommu, &cmd);
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+
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iommu->need_sync = 1;
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- return iommu_queue_command(iommu, &cmd);
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+ return ret;
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}
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/*
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@@ -159,6 +162,7 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
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u64 address, u16 domid, int pde, int s)
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{
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struct iommu_cmd cmd;
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+ int ret;
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memset(&cmd, 0, sizeof(cmd));
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address &= PAGE_MASK;
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@@ -171,9 +175,11 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
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if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
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cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
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+ ret = iommu_queue_command(iommu, &cmd);
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+
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iommu->need_sync = 1;
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- return iommu_queue_command(iommu, &cmd);
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+ return ret;
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}
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/*
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