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@@ -298,7 +298,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
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static int omap2_dflt_clk_enable(struct clk *clk)
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{
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- u32 regval32;
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+ u32 v;
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if (unlikely(clk->enable_reg == NULL)) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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@@ -306,12 +306,12 @@ static int omap2_dflt_clk_enable(struct clk *clk)
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return 0; /* REVISIT: -EINVAL */
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}
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- regval32 = __raw_readl(clk->enable_reg);
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+ v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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- regval32 &= ~(1 << clk->enable_bit);
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+ v &= ~(1 << clk->enable_bit);
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else
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- regval32 |= (1 << clk->enable_bit);
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- __raw_writel(regval32, clk->enable_reg);
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+ v |= (1 << clk->enable_bit);
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+ __raw_writel(v, clk->enable_reg);
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wmb();
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return 0;
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@@ -335,7 +335,7 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk)
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static void omap2_dflt_clk_disable(struct clk *clk)
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{
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- u32 regval32;
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+ u32 v;
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if (!clk->enable_reg) {
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/*
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@@ -347,12 +347,12 @@ static void omap2_dflt_clk_disable(struct clk *clk)
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return;
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}
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- regval32 = __raw_readl(clk->enable_reg);
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+ v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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- regval32 |= (1 << clk->enable_bit);
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+ v |= (1 << clk->enable_bit);
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else
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- regval32 &= ~(1 << clk->enable_bit);
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- __raw_writel(regval32, clk->enable_reg);
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+ v &= ~(1 << clk->enable_bit);
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+ __raw_writel(v, clk->enable_reg);
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wmb();
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}
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@@ -643,23 +643,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
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return clkr->val;
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}
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-/**
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- * omap2_get_clksel - find clksel register addr & field mask for a clk
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- * @clk: struct clk to use
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- * @field_mask: ptr to u32 to store the register field mask
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- *
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- * Returns the address of the clksel register upon success or NULL on error.
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- */
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-static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
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-{
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- if (!clk->clksel_reg || (clk->clksel_mask == 0))
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- return NULL;
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-
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- *field_mask = clk->clksel_mask;
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-
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- return clk->clksel_reg;
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-}
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-
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/**
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* omap2_clksel_get_divisor - get current divider applied to parent clock.
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* @clk: OMAP struct clk to use.
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@@ -668,40 +651,36 @@ static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
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*/
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u32 omap2_clksel_get_divisor(struct clk *clk)
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{
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- u32 field_mask, field_val;
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- void __iomem *div_addr;
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+ u32 v;
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- div_addr = omap2_get_clksel(clk, &field_mask);
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- if (!div_addr)
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+ if (!clk->clksel_mask)
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return 0;
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- field_val = __raw_readl(div_addr) & field_mask;
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- field_val >>= __ffs(field_mask);
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+ v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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+ v >>= __ffs(clk->clksel_mask);
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- return omap2_clksel_to_divisor(clk, field_val);
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+ return omap2_clksel_to_divisor(clk, v);
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}
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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{
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- u32 field_mask, field_val, reg_val, validrate, new_div = 0;
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- void __iomem *div_addr;
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+ u32 v, field_val, validrate, new_div = 0;
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- validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
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- if (validrate != rate)
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+ if (!clk->clksel_mask)
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return -EINVAL;
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- div_addr = omap2_get_clksel(clk, &field_mask);
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- if (!div_addr)
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+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
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+ if (validrate != rate)
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return -EINVAL;
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field_val = omap2_divisor_to_clksel(clk, new_div);
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if (field_val == ~0)
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return -EINVAL;
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- reg_val = __raw_readl(div_addr);
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- reg_val &= ~field_mask;
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- reg_val |= (field_val << __ffs(field_mask));
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- __raw_writel(reg_val, div_addr);
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+ v = __raw_readl(clk->clksel_reg);
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+ v &= ~clk->clksel_mask;
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+ v |= field_val << __ffs(clk->clksel_mask);
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+ __raw_writel(v, clk->clksel_reg);
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wmb();
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clk->rate = clk->parent->rate / new_div;
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@@ -737,18 +716,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
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/*
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* Converts encoded control register address into a full address
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- * On error, *src_addr will be returned as 0.
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+ * On error, the return value (parent_div) will be 0.
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*/
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-static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
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- struct clk *src_clk, u32 *field_mask,
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- struct clk *clk, u32 *parent_div)
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+static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
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+ u32 *field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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- *parent_div = 0;
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- *src_addr = NULL;
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-
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clks = omap2_get_clksel_by_parent(clk, src_clk);
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if (!clks)
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return 0;
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@@ -768,17 +743,14 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
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/* Should never happen. Add a clksel mask to the struct clk. */
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WARN_ON(clk->clksel_mask == 0);
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- *field_mask = clk->clksel_mask;
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- *src_addr = clk->clksel_reg;
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- *parent_div = clkr->div;
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+ *field_val = clkr->val;
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- return clkr->val;
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+ return clkr->div;
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}
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
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{
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- void __iomem *src_addr;
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- u32 field_val, field_mask, reg_val, parent_div;
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+ u32 field_val, v, parent_div;
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if (clk->flags & CONFIG_PARTICIPANT)
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return -EINVAL;
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@@ -786,18 +758,18 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
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if (!clk->clksel)
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return -EINVAL;
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- field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
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- &field_mask, clk, &parent_div);
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- if (!src_addr)
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+ parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
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+ if (!parent_div)
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return -EINVAL;
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if (clk->usecount > 0)
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_omap2_clk_disable(clk);
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/* Set new source value (previous dividers if any in effect) */
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- reg_val = __raw_readl(src_addr) & ~field_mask;
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- reg_val |= (field_val << __ffs(field_mask));
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- __raw_writel(reg_val, src_addr);
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+ v = __raw_readl(clk->clksel_reg);
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+ v &= ~clk->clksel_mask;
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+ v |= field_val << __ffs(clk->clksel_mask);
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+ __raw_writel(v, clk->clksel_reg);
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wmb();
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if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
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