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@@ -48,9 +48,20 @@ int x86_acpi_suspend_lowlevel(void)
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#ifndef CONFIG_64BIT
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native_store_gdt((struct desc_ptr *)&header->pmode_gdt);
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+ /*
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+ * We have to check that we can write back the value, and not
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+ * just read it. At least on 90 nm Pentium M (Family 6, Model
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+ * 13), reading an invalid MSR is not guaranteed to trap, see
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+ * Erratum X4 in "Intel Pentium M Processor on 90 nm Process
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+ * with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90
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+ * nm process with 512-KB L2 Cache Specification Update".
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+ */
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if (!rdmsr_safe(MSR_EFER,
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&header->pmode_efer_low,
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- &header->pmode_efer_high))
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+ &header->pmode_efer_high) &&
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+ !wrmsr_safe(MSR_EFER,
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+ header->pmode_efer_low,
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+ header->pmode_efer_high))
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header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
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#endif /* !CONFIG_64BIT */
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@@ -61,7 +72,10 @@ int x86_acpi_suspend_lowlevel(void)
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}
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if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
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&header->pmode_misc_en_low,
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- &header->pmode_misc_en_high))
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+ &header->pmode_misc_en_high) &&
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+ !wrmsr_safe(MSR_IA32_MISC_ENABLE,
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+ header->pmode_misc_en_low,
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+ header->pmode_misc_en_high))
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header->pmode_behavior |=
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(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
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header->realmode_flags = acpi_realmode_flags;
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