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@@ -16,7 +16,8 @@
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#define DMAE0_IRQ 38
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#define SH_DMAC_BASE0 0xFF608020
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#define SH_DMARS_BASE 0xFF609000
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-#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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+#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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+ defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define DMTE0_IRQ 48 /* DMAC0A*/
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#define DMTE4_IRQ 40 /* DMAC0B */
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#define DMTE6_IRQ 42
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