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@@ -476,6 +476,13 @@ choice
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of the tiles using the RS1 memory map, including all new A-class
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core tiles, FPGA-based SMMs and software models.
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+ config DEBUG_VEXPRESS_UART0_CRX
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+ bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
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+ depends on ARCH_VEXPRESS && !MMU
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+ help
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+ This option selects UART0 at 0xb0090000. This is appropriate for
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+ Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
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+
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config DEBUG_VT8500_UART0
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bool "Use UART0 on VIA/Wondermedia SoCs"
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depends on ARCH_VT8500
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@@ -645,7 +652,8 @@ config DEBUG_LL_INCLUDE
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default "debug/tegra.S" if DEBUG_TEGRA_UART
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default "debug/ux500.S" if DEBUG_UX500_UART
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default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
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- DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
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+ DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \
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+ DEBUG_VEXPRESS_UART0_CRX
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default "debug/vt8500.S" if DEBUG_VT8500_UART0
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default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
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default "mach/debug-macro.S"
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