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@@ -164,7 +164,9 @@ int rs400_gart_enable(struct radeon_device *rdev)
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WREG32(RADEON_BUS_CNTL, tmp);
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WREG32(RADEON_BUS_CNTL, tmp);
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}
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}
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/* Table should be in 32bits address space so ignore bits above. */
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/* Table should be in 32bits address space so ignore bits above. */
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- tmp = rdev->gart.table_addr & 0xfffff000;
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+ tmp = (u32)rdev->gart.table_addr & 0xfffff000;
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+ tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
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+
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WREG32_MC(RS480_GART_BASE, tmp);
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WREG32_MC(RS480_GART_BASE, tmp);
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/* TODO: more tweaking here */
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/* TODO: more tweaking here */
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WREG32_MC(RS480_GART_FEATURE_ID,
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WREG32_MC(RS480_GART_FEATURE_ID,
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@@ -201,10 +203,17 @@ void rs400_gart_disable(struct radeon_device *rdev)
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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{
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+ uint32_t entry;
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+
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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return -EINVAL;
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}
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}
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- rdev->gart.table.ram.ptr[i] = cpu_to_le32(((uint32_t)addr) | 0xC);
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+
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+ entry = (lower_32_bits(addr) & PAGE_MASK) |
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+ ((upper_32_bits(addr) & 0xff) << 4) |
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+ 0xc;
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+ entry = cpu_to_le32(entry);
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+ rdev->gart.table.ram.ptr[i] = entry;
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return 0;
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return 0;
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}
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}
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