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@@ -122,12 +122,15 @@ static enum sci_status
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scic_sds_phy_link_layer_initialization(struct scic_sds_phy *sci_phy,
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struct scu_link_layer_registers __iomem *link_layer_registers)
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{
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- struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
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+ struct scic_sds_controller *scic =
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+ sci_phy->owning_port->owning_controller;
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int phy_idx = sci_phy->phy_index;
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- struct sci_phy_user_params *phy_user = &scic->user_parameters.sds1.phys[phy_idx];
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- struct sci_phy_oem_params *phy_oem = &scic->oem_parameters.sds1.phys[phy_idx];
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+ struct sci_phy_user_params *phy_user =
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+ &scic->user_parameters.sds1.phys[phy_idx];
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+ struct sci_phy_oem_params *phy_oem =
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+ &scic->oem_parameters.sds1.phys[phy_idx];
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u32 phy_configuration;
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- struct sas_capabilities phy_capabilities;
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+ struct scic_phy_cap phy_cap;
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u32 parity_check = 0;
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u32 parity_count = 0;
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u32 llctl, link_rate;
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@@ -146,7 +149,8 @@ scic_sds_phy_link_layer_initialization(struct scic_sds_phy *sci_phy,
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&sci_phy->link_layer_registers->transmit_identification);
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/* Write the device SAS Address */
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- writel(0xFEDCBA98, &sci_phy->link_layer_registers->sas_device_name_high);
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+ writel(0xFEDCBA98,
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+ &sci_phy->link_layer_registers->sas_device_name_high);
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writel(phy_idx, &sci_phy->link_layer_registers->sas_device_name_low);
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/* Write the source SAS Address */
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@@ -170,21 +174,21 @@ scic_sds_phy_link_layer_initialization(struct scic_sds_phy *sci_phy,
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&sci_phy->link_layer_registers->phy_configuration);
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/* Configure the SNW capabilities */
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- phy_capabilities.u.all = 0;
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- phy_capabilities.u.bits.start = 1;
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- phy_capabilities.u.bits.gen3_without_ssc_supported = 1;
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- phy_capabilities.u.bits.gen2_without_ssc_supported = 1;
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- phy_capabilities.u.bits.gen1_without_ssc_supported = 1;
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+ phy_cap.all = 0;
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+ phy_cap.start = 1;
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+ phy_cap.gen3_no_ssc = 1;
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+ phy_cap.gen2_no_ssc = 1;
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+ phy_cap.gen1_no_ssc = 1;
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if (scic->oem_parameters.sds1.controller.do_enable_ssc == true) {
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- phy_capabilities.u.bits.gen3_with_ssc_supported = 1;
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- phy_capabilities.u.bits.gen2_with_ssc_supported = 1;
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- phy_capabilities.u.bits.gen1_with_ssc_supported = 1;
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+ phy_cap.gen3_ssc = 1;
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+ phy_cap.gen2_ssc = 1;
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+ phy_cap.gen1_ssc = 1;
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}
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/*
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* The SAS specification indicates that the phy_capabilities that
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* are transmitted shall have an even parity. Calculate the parity. */
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- parity_check = phy_capabilities.u.all;
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+ parity_check = phy_cap.all;
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while (parity_check != 0) {
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if (parity_check & 0x1)
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parity_count++;
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@@ -195,10 +199,9 @@ scic_sds_phy_link_layer_initialization(struct scic_sds_phy *sci_phy,
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* If parity indicates there are an odd number of bits set, then
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* set the parity bit to 1 in the phy capabilities. */
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if ((parity_count % 2) != 0)
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- phy_capabilities.u.bits.parity = 1;
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+ phy_cap.parity = 1;
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- writel(phy_capabilities.u.all,
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- &sci_phy->link_layer_registers->phy_capabilities);
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+ writel(phy_cap.all, &sci_phy->link_layer_registers->phy_capabilities);
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/* Set the enable spinup period but disable the ability to send
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* notify enable spinup
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@@ -561,7 +564,7 @@ enum sci_status scic_sas_phy_get_properties(
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&sci_phy->phy_type.sas_id_frame,
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sizeof(struct sas_identify_frame));
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- properties->received_capabilities.u.all =
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+ properties->rcvd_cap.all =
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readl(&sci_phy->link_layer_registers->receive_phycap);
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return SCI_SUCCESS;
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