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@@ -62,73 +62,10 @@
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#define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
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#define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
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#define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
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-/*
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- * Interrupt registers.
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- * 64 bit interrupt sources registers ws ced.
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- * sme interupts were removed and new ones were added.
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- * Order was changed.
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- */
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-#define FIQ_MASK (REGISTERS_BASE + 0x0400)
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-#define FIQ_MASK_L (REGISTERS_BASE + 0x0400)
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-#define FIQ_MASK_H (REGISTERS_BASE + 0x0404)
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-#define FIQ_MASK_SET (REGISTERS_BASE + 0x0408)
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-#define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408)
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-#define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C)
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-#define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410)
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-#define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410)
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-#define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414)
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-#define IRQ_MASK (REGISTERS_BASE + 0x0418)
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-#define IRQ_MASK_L (REGISTERS_BASE + 0x0418)
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-#define IRQ_MASK_H (REGISTERS_BASE + 0x041C)
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-#define IRQ_MASK_SET (REGISTERS_BASE + 0x0420)
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-#define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420)
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-#define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424)
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-#define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428)
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-#define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428)
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-#define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C)
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-#define ECPU_MASK (REGISTERS_BASE + 0x0448)
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-#define FIQ_STS_L (REGISTERS_BASE + 0x044C)
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-#define FIQ_STS_H (REGISTERS_BASE + 0x0450)
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-#define IRQ_STS_L (REGISTERS_BASE + 0x0454)
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-#define IRQ_STS_H (REGISTERS_BASE + 0x0458)
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-#define INT_STS_ND (REGISTERS_BASE + 0x0464)
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-#define INT_STS_RAW_L (REGISTERS_BASE + 0x0464)
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-#define INT_STS_RAW_H (REGISTERS_BASE + 0x0468)
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-#define INT_STS_CLR (REGISTERS_BASE + 0x04B4)
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-#define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4)
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-#define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8)
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-#define INT_ACK (REGISTERS_BASE + 0x046C)
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-#define INT_ACK_L (REGISTERS_BASE + 0x046C)
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-#define INT_ACK_H (REGISTERS_BASE + 0x0470)
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-#define INT_TRIG (REGISTERS_BASE + 0x0474)
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-#define INT_TRIG_L (REGISTERS_BASE + 0x0474)
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-#define INT_TRIG_H (REGISTERS_BASE + 0x0478)
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-#define HOST_STS_L (REGISTERS_BASE + 0x045C)
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-#define HOST_STS_H (REGISTERS_BASE + 0x0460)
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-#define HOST_MASK (REGISTERS_BASE + 0x0430)
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-#define HOST_MASK_L (REGISTERS_BASE + 0x0430)
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-#define HOST_MASK_H (REGISTERS_BASE + 0x0434)
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-#define HOST_MASK_SET (REGISTERS_BASE + 0x0438)
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-#define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438)
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-#define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C)
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-#define HOST_MASK_CLR (REGISTERS_BASE + 0x0440)
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-#define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440)
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-#define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444)
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#define ACX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
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#define ACX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
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-/* Host Interrupts*/
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-#define HINT_MASK (REGISTERS_BASE + 0x0494)
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-#define HINT_MASK_SET (REGISTERS_BASE + 0x0498)
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-#define HINT_MASK_CLR (REGISTERS_BASE + 0x049C)
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-#define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04A0)
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-/*1150 spec calls this HINT_STS_RAW*/
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-#define HINT_STS_ND (REGISTERS_BASE + 0x04B0)
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-#define HINT_STS_CLR (REGISTERS_BASE + 0x04A4)
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-#define HINT_ACK (REGISTERS_BASE + 0x04A8)
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-#define HINT_TRIG (REGISTERS_BASE + 0x04AC)
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-
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/*=============================================
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Host Interrupt Mask Register - 32bit (RW)
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------------------------------------------
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@@ -432,16 +369,6 @@
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| CFG_RX_PRSP_EN)
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-/*===============================================
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- Phy regs
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- ===============================================*/
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-#define ACX_PHY_ADDR_REG SBB_ADDR
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-#define ACX_PHY_DATA_REG SBB_DATA
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-#define ACX_PHY_CTRL_REG SBB_CTL
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-#define ACX_PHY_REG_WR_MASK 0x00000001ul
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-#define ACX_PHY_REG_RD_MASK 0x00000002ul
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-
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-
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/*===============================================
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EEPROM Read/Write Request 32bit RW
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------------------------------------------
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@@ -511,28 +438,6 @@
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#define ACX_CONT_WIND_MIN_MASK 0x0000007f
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#define ACX_CONT_WIND_MAX 0x03ff0000
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-/*
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- * Indirect slave register/memory registers
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- * ----------------------------------------
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- */
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-#define HW_SLAVE_REG_ADDR_REG 0x00000004
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-#define HW_SLAVE_REG_DATA_REG 0x00000008
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-#define HW_SLAVE_REG_CTRL_REG 0x0000000c
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-
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-#define SLAVE_AUTO_INC 0x00010000
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-#define SLAVE_NO_AUTO_INC 0x00000000
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-#define SLAVE_HOST_LITTLE_ENDIAN 0x00000000
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-
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-#define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR
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-#define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA
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-#define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL
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-#define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL
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-
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-#define HW_FUNC_EVENT_INT_EN 0x8000
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-#define HW_FUNC_EVENT_MASK_REG 0x00000034
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-
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-#define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP)
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-
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/*===============================================
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HI_CFG Interface Configuration Register Values
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------------------------------------------
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@@ -647,10 +552,6 @@ b12-b0 - Supported Rate indicator bits as defined below.
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******************************************************************************/
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-#define TNETW1251_CHIP_ID_PG1_0 0x07010101
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-#define TNETW1251_CHIP_ID_PG1_1 0x07020101
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-#define TNETW1251_CHIP_ID_PG1_2 0x07030101
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-
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/*************************************************************************
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Interrupt Trigger Register (Host -> WiLink)
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Luis R. Rodriguez