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@@ -333,7 +333,6 @@ static inline int numcol(u32 col)
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return cols[col & 0x3];
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}
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-
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/****************************************************************************
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Memory check routines
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****************************************************************************/
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@@ -355,6 +354,23 @@ static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
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return NULL;
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}
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+/**
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+ * i7core_get_active_channels() - gets the number of channels and csrows
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+ * @socket: Quick Path Interconnect socket
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+ * @channels: Number of channels that will be returned
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+ * @csrows: Number of csrows found
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+ *
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+ * Since EDAC core needs to know in advance the number of available channels
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+ * and csrows, in order to allocate memory for csrows/channels, it is needed
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+ * to run two similar steps. At the first step, implemented on this function,
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+ * it checks the number of csrows/channels present at one socket.
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+ * this is used in order to properly allocate the size of mci components.
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+ *
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+ * It should be noticed that none of the current available datasheets explain
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+ * or even mention how csrows are seen by the memory controller. So, we need
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+ * to add a fake description for csrows.
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+ * So, this driver is attributing one DIMM memory for one csrow.
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+ */
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static int i7core_get_active_channels(u8 socket, unsigned *channels,
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unsigned *csrows)
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{
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