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@@ -1172,6 +1172,8 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
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int ath5k_hw_on_hold(struct ath5k_hw *ah);
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int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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struct ieee80211_channel *channel, bool change_channel);
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+int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
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+ bool is_set);
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/* Power management functions */
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/* DMA Related Functions */
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@@ -1328,29 +1330,6 @@ static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
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iowrite32(val, ah->ah_iobase + reg);
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}
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-#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
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-/*
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- * Check if a register write has been completed
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- */
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-static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
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- u32 val, bool is_set)
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-{
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- int i;
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- u32 data;
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-
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- for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
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- data = ath5k_hw_reg_read(ah, reg);
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- if (is_set && (data & flag))
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- break;
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- else if ((data & flag) == val)
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- break;
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- udelay(15);
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- }
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-
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- return (i <= 0) ? -EAGAIN : 0;
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-}
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-#endif
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-
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static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
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{
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u32 retval = 0, bit, i;
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