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@@ -19,68 +19,160 @@ _b43_declare_plcp_hdr(6);
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#undef _b43_declare_plcp_hdr
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/* TX header for v4 firmware */
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-struct b43_txhdr_fw4 {
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- __le32 mac_ctl; /* MAC TX control */
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- __le16 mac_frame_ctl; /* Copy of the FrameControl field */
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+struct b43_txhdr {
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+ __le32 mac_ctl; /* MAC TX control */
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+ __le16 mac_frame_ctl; /* Copy of the FrameControl field */
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__le16 tx_fes_time_norm; /* TX FES Time Normal */
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- __le16 phy_ctl; /* PHY TX control */
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- __le16 phy_ctl_0; /* Unused */
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- __le16 phy_ctl_1; /* Unused */
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- __le16 phy_ctl_rts_0; /* Unused */
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- __le16 phy_ctl_rts_1; /* Unused */
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- __u8 phy_rate; /* PHY rate */
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- __u8 phy_rate_rts; /* PHY rate for RTS/CTS */
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- __u8 extra_ft; /* Extra Frame Types */
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- __u8 chan_radio_code; /* Channel Radio Code */
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- __u8 iv[16]; /* Encryption IV */
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- __u8 tx_receiver[6]; /* TX Frame Receiver address */
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- __le16 tx_fes_time_fb; /* TX FES Time Fallback */
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- struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */
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- __le16 rts_dur_fb; /* RTS fallback duration */
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- struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP */
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- __le16 dur_fb; /* Fallback duration */
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- __le16 mm_dur_time; /* Unused */
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- __le16 mm_dur_time_fb; /* Unused */
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- __le32 time_stamp; /* Timestamp */
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- PAD_BYTES(2);
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- __le16 cookie; /* TX frame cookie */
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- __le16 tx_status; /* TX status */
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- struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP */
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- __u8 rts_frame[16]; /* The RTS frame (if used) */
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- PAD_BYTES(2);
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- struct b43_plcp_hdr6 plcp; /* Main PLCP */
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+ __le16 phy_ctl; /* PHY TX control */
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+ __le16 phy_ctl1; /* PHY TX control word 1 */
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+ __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */
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+ __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */
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+ __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */
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+ __u8 phy_rate; /* PHY rate */
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+ __u8 phy_rate_rts; /* PHY rate for RTS/CTS */
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+ __u8 extra_ft; /* Extra Frame Types */
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+ __u8 chan_radio_code; /* Channel Radio Code */
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+ __u8 iv[16]; /* Encryption IV */
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+ __u8 tx_receiver[6]; /* TX Frame Receiver address */
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+ __le16 tx_fes_time_fb; /* TX FES Time Fallback */
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+ struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
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+ __le16 rts_dur_fb; /* RTS fallback duration */
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+ struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */
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+ __le16 dur_fb; /* Fallback duration */
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+ __le16 mimo_modelen; /* MIMO mode length */
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+ __le16 mimo_ratelen_fb; /* MIMO fallback rate length */
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+ __le32 timeout; /* Timeout */
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+
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+ union {
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+ /* The new r410 format. */
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+ struct {
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+ __le16 mimo_antenna; /* MIMO antenna select */
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+ __le16 preload_size; /* Preload size */
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+ PAD_BYTES(2);
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+ __le16 cookie; /* TX frame cookie */
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+ __le16 tx_status; /* TX status */
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+ struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
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+ __u8 rts_frame[16]; /* The RTS frame (if used) */
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+ PAD_BYTES(2);
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+ struct b43_plcp_hdr6 plcp; /* Main PLCP header */
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+ } new_format __attribute__ ((__packed__));
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+
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+ /* The old r351 format. */
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+ struct {
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+ PAD_BYTES(2);
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+ __le16 cookie; /* TX frame cookie */
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+ __le16 tx_status; /* TX status */
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+ struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
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+ __u8 rts_frame[16]; /* The RTS frame (if used) */
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+ PAD_BYTES(2);
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+ struct b43_plcp_hdr6 plcp; /* Main PLCP header */
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+ } old_format __attribute__ ((__packed__));
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+
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+ } __attribute__ ((__packed__));
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} __attribute__ ((__packed__));
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/* MAC TX control */
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-#define B43_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
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-#define B43_TX4_MAC_KEYIDX_SHIFT 20
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-#define B43_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
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-#define B43_TX4_MAC_KEYALG_SHIFT 16
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-#define B43_TX4_MAC_LIFETIME 0x00001000
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-#define B43_TX4_MAC_FRAMEBURST 0x00000800
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-#define B43_TX4_MAC_SENDCTS 0x00000400
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-#define B43_TX4_MAC_AMPDU 0x00000300
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-#define B43_TX4_MAC_AMPDU_SHIFT 8
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-#define B43_TX4_MAC_5GHZ 0x00000080
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-#define B43_TX4_MAC_IGNPMQ 0x00000020
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-#define B43_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
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-#define B43_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
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-#define B43_TX4_MAC_SENDRTS 0x00000004
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-#define B43_TX4_MAC_LONGFRAME 0x00000002
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-#define B43_TX4_MAC_ACK 0x00000001
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+#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
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+#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
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+#define B43_TXH_MAC_KEYIDX_SHIFT 20
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+#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
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+#define B43_TXH_MAC_KEYALG_SHIFT 16
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+#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
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+#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
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+#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
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+#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
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+#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
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+#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
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+#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
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+#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
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+#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
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+#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
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+#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
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+#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
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+#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
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+#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
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+#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
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+#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
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+#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
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+#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
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+#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
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/* Extra Frame Types */
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-#define B43_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */
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-#define B43_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
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-#define B43_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
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+#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
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+#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
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+#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
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+#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
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+#define B43_TXH_EFT_FB_N 0x03 /* N */
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+#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
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+#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
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+#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
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+#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
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+#define B43_TXH_EFT_RTS_N 0x0C /* N */
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+#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
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+#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
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+#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
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+#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
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+#define B43_TXH_EFT_RTSFB_N 0x30 /* N */
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/* PHY TX control word */
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-#define B43_TX4_PHY_OFDM 0x0001 /* Data frame rate type */
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-#define B43_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
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-#define B43_TX4_PHY_ANT 0x03C0 /* Antenna selection */
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-#define B43_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
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-#define B43_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
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-#define B43_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
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+#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
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+#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
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+#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
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+#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
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+#define B43_TXH_PHY_ENC_N 0x0003 /* N */
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+#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
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+#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
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+#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
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+#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
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+#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
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+#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
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+#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
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+#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
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+#define B43_TXH_PHY_TXPWR_SHIFT 10
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+
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+/* PHY TX control word 1 */
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+#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
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+#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
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+#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
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+#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
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+#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
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+#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
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+#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
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+#define B43_TXH_PHY1_MODE 0x0038 /* Mode */
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+#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
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+#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
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+#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
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+#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
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+#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
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+#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
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+#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
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+#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
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+#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
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+#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
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+#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
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+#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
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+#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
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+#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
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+#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
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+#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
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+#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
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+
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+
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+/* r351 firmware compatibility stuff. */
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+static inline
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+bool b43_is_old_txhdr_format(struct b43_wldev *dev)
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+{
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+ return (dev->fw.rev <= 351);
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+}
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+
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+static inline
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+size_t b43_txhdr_size(struct b43_wldev *dev)
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+{
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+ if (b43_is_old_txhdr_format(dev))
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+ return 100 + sizeof(struct b43_plcp_hdr6);
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+ return 104 + sizeof(struct b43_plcp_hdr6);
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+}
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+
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void b43_generate_txhdr(struct b43_wldev *dev,
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u8 * txhdr,
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Michael Buesch