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@@ -2,7 +2,6 @@
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*
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*
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* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
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* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
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*
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*
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- * $Id: slichw.h,v 1.3 2008/03/17 19:27:26 chris Exp $
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* modification, are permitted provided that the following conditions
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@@ -236,110 +235,106 @@
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#define TRUE 1
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#define TRUE 1
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#endif
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#endif
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-typedef struct _slic_rcvbuf_t {
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- uchar pad1[6];
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+struct slic_rcvbuf {
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+ unsigned char pad1[6];
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ushort pad2;
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ushort pad2;
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- ulong32 pad3;
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- ulong32 pad4;
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- ulong32 buffer;
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- ulong32 length;
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- ulong32 status;
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- ulong32 pad5;
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+ u32 pad3;
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+ u32 pad4;
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+ u32 buffer;
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+ u32 length;
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+ u32 status;
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+ u32 pad5;
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ushort pad6;
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ushort pad6;
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- uchar data[SLIC_RCVBUF_DATASIZE];
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-} slic_rcvbuf_t, *p_slic_rcvbuf_t;
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+ unsigned char data[SLIC_RCVBUF_DATASIZE];
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+};
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-typedef struct _slic_hddr_wds {
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+ struct slic_hddr_wds {
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union {
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union {
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struct {
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struct {
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- ulong32 frame_status;
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- ulong32 frame_status_b;
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- ulong32 time_stamp;
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- ulong32 checksum;
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+ u32 frame_status;
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+ u32 frame_status_b;
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+ u32 time_stamp;
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+ u32 checksum;
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} hdrs_14port;
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} hdrs_14port;
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struct {
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struct {
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- ulong32 frame_status;
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+ u32 frame_status;
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ushort ByteCnt;
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ushort ByteCnt;
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ushort TpChksum;
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ushort TpChksum;
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ushort CtxHash;
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ushort CtxHash;
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ushort MacHash;
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ushort MacHash;
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- ulong32 BufLnk;
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+ u32 BufLnk;
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} hdrs_gbit;
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} hdrs_gbit;
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} u0;
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} u0;
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-} slic_hddr_wds_t, *p_slic_hddr_wds;
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+};
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#define frame_status14 u0.hdrs_14port.frame_status
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#define frame_status14 u0.hdrs_14port.frame_status
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#define frame_status_b14 u0.hdrs_14port.frame_status_b
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#define frame_status_b14 u0.hdrs_14port.frame_status_b
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#define frame_statusGB u0.hdrs_gbit.frame_status
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#define frame_statusGB u0.hdrs_gbit.frame_status
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-typedef struct _slic_host64sg_t {
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- ulong32 paddrl;
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- ulong32 paddrh;
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- ulong32 length;
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-} slic_host64sg_t, *p_slic_host64sg_t;
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-
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-typedef struct _slic_host64_cmd_t {
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- ulong32 hosthandle;
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- ulong32 RSVD;
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- uchar command;
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- uchar flags;
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+struct slic_host64sg {
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+ u32 paddrl;
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+ u32 paddrh;
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+ u32 length;
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+};
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+
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+struct slic_host64_cmd {
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+ u32 hosthandle;
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+ u32 RSVD;
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+ unsigned char command;
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+ unsigned char flags;
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union {
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union {
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ushort rsv1;
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ushort rsv1;
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ushort rsv2;
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ushort rsv2;
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} u0;
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} u0;
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union {
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union {
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struct {
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struct {
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- ulong32 totlen;
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- slic_host64sg_t bufs[SLIC_MAX64_BCNT];
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+ u32 totlen;
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+ struct slic_host64sg bufs[SLIC_MAX64_BCNT];
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} slic_buffers;
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} slic_buffers;
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} u;
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} u;
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+};
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-} slic_host64_cmd_t, *p_slic_host64_cmd_t;
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+struct slic_rspbuf {
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+ u32 hosthandle;
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+ u32 pad0;
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+ u32 pad1;
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+ u32 status;
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+ u32 pad2[4];
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-typedef struct _slic_rspbuf_t {
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- ulong32 hosthandle;
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- ulong32 pad0;
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- ulong32 pad1;
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- ulong32 status;
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- ulong32 pad2[4];
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+};
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-} slic_rspbuf_t, *p_slic_rspbuf_t;
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+struct slic_regs {
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+ u32 slic_reset; /* Reset Register */
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+ u32 pad0;
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-typedef ulong32 SLIC_REG;
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-
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-
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-typedef struct _slic_regs_t {
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- ULONG slic_reset; /* Reset Register */
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- ULONG pad0;
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-
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- ULONG slic_icr; /* Interrupt Control Register */
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- ULONG pad2;
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+ u32 slic_icr; /* Interrupt Control Register */
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+ u32 pad2;
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#define SLIC_ICR 0x0008
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#define SLIC_ICR 0x0008
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- ULONG slic_isp; /* Interrupt status pointer */
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- ULONG pad1;
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+ u32 slic_isp; /* Interrupt status pointer */
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+ u32 pad1;
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#define SLIC_ISP 0x0010
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#define SLIC_ISP 0x0010
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- ULONG slic_isr; /* Interrupt status */
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- ULONG pad3;
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+ u32 slic_isr; /* Interrupt status */
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+ u32 pad3;
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#define SLIC_ISR 0x0018
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#define SLIC_ISR 0x0018
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- SLIC_REG slic_hbar; /* Header buffer address reg */
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- ULONG pad4;
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+ u32 slic_hbar; /* Header buffer address reg */
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+ u32 pad4;
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/* 31-8 - phy addr of set of contiguous hdr buffers
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/* 31-8 - phy addr of set of contiguous hdr buffers
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7-0 - number of buffers passed
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7-0 - number of buffers passed
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Buffers are 256 bytes long on 256-byte boundaries. */
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Buffers are 256 bytes long on 256-byte boundaries. */
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#define SLIC_HBAR 0x0020
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#define SLIC_HBAR 0x0020
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#define SLIC_HBAR_CNT_MSK 0x000000FF
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#define SLIC_HBAR_CNT_MSK 0x000000FF
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- SLIC_REG slic_dbar; /* Data buffer handle & address reg */
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- ULONG pad5;
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+ u32 slic_dbar; /* Data buffer handle & address reg */
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+ u32 pad5;
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/* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
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/* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
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#define SLIC_DBAR 0x0028
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#define SLIC_DBAR 0x0028
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#define SLIC_DBAR_SIZE 2048
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#define SLIC_DBAR_SIZE 2048
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- SLIC_REG slic_cbar; /* Xmt Cmd buf addr regs.*/
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+ u32 slic_cbar; /* Xmt Cmd buf addr regs.*/
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/* 1 per XMT interface
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/* 1 per XMT interface
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31-5 - phy addr of host command buffer
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31-5 - phy addr of host command buffer
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4-0 - length of cmd in multiples of 32 bytes
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4-0 - length of cmd in multiples of 32 bytes
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@@ -348,13 +343,13 @@ typedef struct _slic_regs_t {
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#define SLIC_CBAR_LEN_MSK 0x0000001F
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#define SLIC_CBAR_LEN_MSK 0x0000001F
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#define SLIC_CBAR_ALIGN 0x00000020
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#define SLIC_CBAR_ALIGN 0x00000020
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- SLIC_REG slic_wcs; /* write control store*/
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+ u32 slic_wcs; /* write control store*/
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#define SLIC_WCS 0x0034
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#define SLIC_WCS 0x0034
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#define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
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#define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
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#define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
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#define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
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- SLIC_REG slic_rbar; /* Response buffer address reg.*/
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- ULONG pad7;
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+ u32 slic_rbar; /* Response buffer address reg.*/
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+ u32 pad7;
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/*31-8 - phy addr of set of contiguous response buffers
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/*31-8 - phy addr of set of contiguous response buffers
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7-0 - number of buffers passed
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7-0 - number of buffers passed
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Buffers are 32 bytes long on 32-byte boundaries.*/
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Buffers are 32 bytes long on 32-byte boundaries.*/
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@@ -362,166 +357,166 @@ typedef struct _slic_regs_t {
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#define SLIC_RBAR_CNT_MSK 0x000000FF
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#define SLIC_RBAR_CNT_MSK 0x000000FF
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#define SLIC_RBAR_SIZE 32
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#define SLIC_RBAR_SIZE 32
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- SLIC_REG slic_stats; /* read statistics (UPR) */
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- ULONG pad8;
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+ u32 slic_stats; /* read statistics (UPR) */
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+ u32 pad8;
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#define SLIC_RSTAT 0x0040
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#define SLIC_RSTAT 0x0040
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- SLIC_REG slic_rlsr; /* read link status */
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- ULONG pad9;
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+ u32 slic_rlsr; /* read link status */
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+ u32 pad9;
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#define SLIC_LSTAT 0x0048
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#define SLIC_LSTAT 0x0048
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- SLIC_REG slic_wmcfg; /* Write Mac Config */
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- ULONG pad10;
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+ u32 slic_wmcfg; /* Write Mac Config */
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+ u32 pad10;
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#define SLIC_WMCFG 0x0050
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#define SLIC_WMCFG 0x0050
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- SLIC_REG slic_wphy; /* Write phy register */
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- ULONG pad11;
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+ u32 slic_wphy; /* Write phy register */
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+ u32 pad11;
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#define SLIC_WPHY 0x0058
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#define SLIC_WPHY 0x0058
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- SLIC_REG slic_rcbar; /*Rcv Cmd buf addr reg*/
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- ULONG pad12;
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+ u32 slic_rcbar; /*Rcv Cmd buf addr reg*/
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+ u32 pad12;
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#define SLIC_RCBAR 0x0060
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#define SLIC_RCBAR 0x0060
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- SLIC_REG slic_rconfig; /* Read SLIC Config*/
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- ULONG pad13;
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+ u32 slic_rconfig; /* Read SLIC Config*/
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+ u32 pad13;
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#define SLIC_RCONFIG 0x0068
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#define SLIC_RCONFIG 0x0068
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- SLIC_REG slic_intagg; /* Interrupt aggregation time*/
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- ULONG pad14;
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+ u32 slic_intagg; /* Interrupt aggregation time*/
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+ u32 pad14;
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#define SLIC_INTAGG 0x0070
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#define SLIC_INTAGG 0x0070
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- SLIC_REG slic_wxcfg; /* Write XMIT config reg*/
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- ULONG pad16;
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+ u32 slic_wxcfg; /* Write XMIT config reg*/
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+ u32 pad16;
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#define SLIC_WXCFG 0x0078
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#define SLIC_WXCFG 0x0078
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- SLIC_REG slic_wrcfg; /* Write RCV config reg*/
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- ULONG pad17;
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+ u32 slic_wrcfg; /* Write RCV config reg*/
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+ u32 pad17;
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#define SLIC_WRCFG 0x0080
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#define SLIC_WRCFG 0x0080
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- SLIC_REG slic_wraddral; /* Write rcv addr a low*/
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- ULONG pad18;
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+ u32 slic_wraddral; /* Write rcv addr a low*/
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+ u32 pad18;
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#define SLIC_WRADDRAL 0x0088
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#define SLIC_WRADDRAL 0x0088
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- SLIC_REG slic_wraddrah; /* Write rcv addr a high*/
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- ULONG pad19;
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+ u32 slic_wraddrah; /* Write rcv addr a high*/
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+ u32 pad19;
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#define SLIC_WRADDRAH 0x0090
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#define SLIC_WRADDRAH 0x0090
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- SLIC_REG slic_wraddrbl; /* Write rcv addr b low*/
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- ULONG pad20;
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+ u32 slic_wraddrbl; /* Write rcv addr b low*/
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+ u32 pad20;
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#define SLIC_WRADDRBL 0x0098
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#define SLIC_WRADDRBL 0x0098
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- SLIC_REG slic_wraddrbh; /* Write rcv addr b high*/
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- ULONG pad21;
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+ u32 slic_wraddrbh; /* Write rcv addr b high*/
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+ u32 pad21;
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#define SLIC_WRADDRBH 0x00a0
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#define SLIC_WRADDRBH 0x00a0
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- SLIC_REG slic_mcastlow; /* Low bits of mcast mask*/
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- ULONG pad22;
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+ u32 slic_mcastlow; /* Low bits of mcast mask*/
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+ u32 pad22;
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#define SLIC_MCASTLOW 0x00a8
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#define SLIC_MCASTLOW 0x00a8
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- SLIC_REG slic_mcasthigh; /* High bits of mcast mask*/
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- ULONG pad23;
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+ u32 slic_mcasthigh; /* High bits of mcast mask*/
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+ u32 pad23;
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#define SLIC_MCASTHIGH 0x00b0
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#define SLIC_MCASTHIGH 0x00b0
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- SLIC_REG slic_ping; /* Ping the card*/
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- ULONG pad24;
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+ u32 slic_ping; /* Ping the card*/
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+ u32 pad24;
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#define SLIC_PING 0x00b8
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#define SLIC_PING 0x00b8
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- SLIC_REG slic_dump_cmd; /* Dump command */
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- ULONG pad25;
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+ u32 slic_dump_cmd; /* Dump command */
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+ u32 pad25;
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#define SLIC_DUMP_CMD 0x00c0
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#define SLIC_DUMP_CMD 0x00c0
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- SLIC_REG slic_dump_data; /* Dump data pointer */
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- ULONG pad26;
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+ u32 slic_dump_data; /* Dump data pointer */
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+ u32 pad26;
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#define SLIC_DUMP_DATA 0x00c8
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#define SLIC_DUMP_DATA 0x00c8
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- SLIC_REG slic_pcistatus; /* Read card's pci_status register */
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- ULONG pad27;
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+ u32 slic_pcistatus; /* Read card's pci_status register */
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+ u32 pad27;
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#define SLIC_PCISTATUS 0x00d0
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#define SLIC_PCISTATUS 0x00d0
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- SLIC_REG slic_wrhostid; /* Write hostid field */
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- ULONG pad28;
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+ u32 slic_wrhostid; /* Write hostid field */
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+ u32 pad28;
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#define SLIC_WRHOSTID 0x00d8
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#define SLIC_WRHOSTID 0x00d8
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#define SLIC_RDHOSTID_1GB 0x1554
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#define SLIC_RDHOSTID_1GB 0x1554
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#define SLIC_RDHOSTID_2GB 0x1554
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#define SLIC_RDHOSTID_2GB 0x1554
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- SLIC_REG slic_low_power; /* Put card in a low power state */
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- ULONG pad29;
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+ u32 slic_low_power; /* Put card in a low power state */
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+ u32 pad29;
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#define SLIC_LOW_POWER 0x00e0
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#define SLIC_LOW_POWER 0x00e0
|
|
|
|
|
|
- SLIC_REG slic_quiesce; /* force slic into quiescent state
|
|
|
|
|
|
+ u32 slic_quiesce; /* force slic into quiescent state
|
|
before soft reset */
|
|
before soft reset */
|
|
- ULONG pad30;
|
|
|
|
|
|
+ u32 pad30;
|
|
#define SLIC_QUIESCE 0x00e8
|
|
#define SLIC_QUIESCE 0x00e8
|
|
|
|
|
|
- SLIC_REG slic_reset_iface; /* reset interface queues */
|
|
|
|
- ULONG pad31;
|
|
|
|
|
|
+ u32 slic_reset_iface; /* reset interface queues */
|
|
|
|
+ u32 pad31;
|
|
#define SLIC_RESET_IFACE 0x00f0
|
|
#define SLIC_RESET_IFACE 0x00f0
|
|
|
|
|
|
- SLIC_REG slic_addr_upper; /* Bits 63-32 for host i/f addrs */
|
|
|
|
- ULONG pad32;
|
|
|
|
|
|
+ u32 slic_addr_upper; /* Bits 63-32 for host i/f addrs */
|
|
|
|
+ u32 pad32;
|
|
#define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
|
|
#define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
|
|
|
|
|
|
- SLIC_REG slic_hbar64; /* 64 bit Header buffer address reg */
|
|
|
|
- ULONG pad33;
|
|
|
|
|
|
+ u32 slic_hbar64; /* 64 bit Header buffer address reg */
|
|
|
|
+ u32 pad33;
|
|
#define SLIC_HBAR64 0x0100
|
|
#define SLIC_HBAR64 0x0100
|
|
|
|
|
|
- SLIC_REG slic_dbar64; /* 64 bit Data buffer handle & address reg */
|
|
|
|
- ULONG pad34;
|
|
|
|
|
|
+ u32 slic_dbar64; /* 64 bit Data buffer handle & address reg */
|
|
|
|
+ u32 pad34;
|
|
#define SLIC_DBAR64 0x0108
|
|
#define SLIC_DBAR64 0x0108
|
|
|
|
|
|
- SLIC_REG slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */
|
|
|
|
- ULONG pad35;
|
|
|
|
|
|
+ u32 slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */
|
|
|
|
+ u32 pad35;
|
|
#define SLIC_CBAR64 0x0110
|
|
#define SLIC_CBAR64 0x0110
|
|
|
|
|
|
- SLIC_REG slic_rbar64; /* 64 bit Response buffer address reg.*/
|
|
|
|
- ULONG pad36;
|
|
|
|
|
|
+ u32 slic_rbar64; /* 64 bit Response buffer address reg.*/
|
|
|
|
+ u32 pad36;
|
|
#define SLIC_RBAR64 0x0118
|
|
#define SLIC_RBAR64 0x0118
|
|
|
|
|
|
- SLIC_REG slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/
|
|
|
|
- ULONG pad37;
|
|
|
|
|
|
+ u32 slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/
|
|
|
|
+ u32 pad37;
|
|
#define SLIC_RCBAR64 0x0120
|
|
#define SLIC_RCBAR64 0x0120
|
|
|
|
|
|
- SLIC_REG slic_stats64; /*read statistics (64 bit UPR)*/
|
|
|
|
- ULONG pad38;
|
|
|
|
|
|
+ u32 slic_stats64; /*read statistics (64 bit UPR)*/
|
|
|
|
+ u32 pad38;
|
|
#define SLIC_RSTAT64 0x0128
|
|
#define SLIC_RSTAT64 0x0128
|
|
|
|
|
|
- SLIC_REG slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/
|
|
|
|
- ULONG pad39;
|
|
|
|
|
|
+ u32 slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/
|
|
|
|
+ u32 pad39;
|
|
#define SLIC_RCV_WCS 0x0130
|
|
#define SLIC_RCV_WCS 0x0130
|
|
#define SLIC_RCVWCS_BEGIN 0x40000000
|
|
#define SLIC_RCVWCS_BEGIN 0x40000000
|
|
#define SLIC_RCVWCS_FINISH 0x80000000
|
|
#define SLIC_RCVWCS_FINISH 0x80000000
|
|
|
|
|
|
- SLIC_REG slic_wrvlanid; /* Write VlanId field */
|
|
|
|
- ULONG pad40;
|
|
|
|
|
|
+ u32 slic_wrvlanid; /* Write VlanId field */
|
|
|
|
+ u32 pad40;
|
|
#define SLIC_WRVLANID 0x0138
|
|
#define SLIC_WRVLANID 0x0138
|
|
|
|
|
|
- SLIC_REG slic_read_xf_info; /* Read Transformer info */
|
|
|
|
- ULONG pad41;
|
|
|
|
|
|
+ u32 slic_read_xf_info; /* Read Transformer info */
|
|
|
|
+ u32 pad41;
|
|
#define SLIC_READ_XF_INFO 0x0140
|
|
#define SLIC_READ_XF_INFO 0x0140
|
|
|
|
|
|
- SLIC_REG slic_write_xf_info; /* Write Transformer info */
|
|
|
|
- ULONG pad42;
|
|
|
|
|
|
+ u32 slic_write_xf_info; /* Write Transformer info */
|
|
|
|
+ u32 pad42;
|
|
#define SLIC_WRITE_XF_INFO 0x0148
|
|
#define SLIC_WRITE_XF_INFO 0x0148
|
|
|
|
|
|
- SLIC_REG RSVD1; /* TOE Only */
|
|
|
|
- ULONG pad43;
|
|
|
|
|
|
+ u32 RSVD1; /* TOE Only */
|
|
|
|
+ u32 pad43;
|
|
|
|
|
|
- SLIC_REG RSVD2; /* TOE Only */
|
|
|
|
- ULONG pad44;
|
|
|
|
|
|
+ u32 RSVD2; /* TOE Only */
|
|
|
|
+ u32 pad44;
|
|
|
|
|
|
- SLIC_REG RSVD3; /* TOE Only */
|
|
|
|
- ULONG pad45;
|
|
|
|
|
|
+ u32 RSVD3; /* TOE Only */
|
|
|
|
+ u32 pad45;
|
|
|
|
|
|
- SLIC_REG RSVD4; /* TOE Only */
|
|
|
|
- ULONG pad46;
|
|
|
|
|
|
+ u32 RSVD4; /* TOE Only */
|
|
|
|
+ u32 pad46;
|
|
|
|
|
|
- SLIC_REG slic_ticks_per_sec; /* Write card ticks per second */
|
|
|
|
- ULONG pad47;
|
|
|
|
|
|
+ u32 slic_ticks_per_sec; /* Write card ticks per second */
|
|
|
|
+ u32 pad47;
|
|
#define SLIC_TICKS_PER_SEC 0x0170
|
|
#define SLIC_TICKS_PER_SEC 0x0170
|
|
|
|
|
|
-} __iomem slic_regs_t, *p_slic_regs_t, SLIC_REGS, *PSLIC_REGS;
|
|
|
|
|
|
+};
|
|
|
|
|
|
-typedef enum _UPR_REQUEST {
|
|
|
|
|
|
+enum UPR_REQUEST {
|
|
SLIC_UPR_STATS,
|
|
SLIC_UPR_STATS,
|
|
SLIC_UPR_RLSR,
|
|
SLIC_UPR_RLSR,
|
|
SLIC_UPR_WCFG,
|
|
SLIC_UPR_WCFG,
|
|
@@ -532,103 +527,102 @@ typedef enum _UPR_REQUEST {
|
|
SLIC_UPR_PDWN,
|
|
SLIC_UPR_PDWN,
|
|
SLIC_UPR_PING,
|
|
SLIC_UPR_PING,
|
|
SLIC_UPR_DUMP,
|
|
SLIC_UPR_DUMP,
|
|
-} UPR_REQUEST;
|
|
|
|
-
|
|
|
|
-typedef struct _inicpm_wakepattern {
|
|
|
|
- ulong32 patternlength;
|
|
|
|
- uchar pattern[SLIC_PM_PATTERNSIZE];
|
|
|
|
- uchar mask[SLIC_PM_PATTERNSIZE];
|
|
|
|
-} inicpm_wakepattern_t, *p_inicpm_wakepattern_t;
|
|
|
|
-
|
|
|
|
-typedef struct _inicpm_state {
|
|
|
|
- ulong32 powercaps;
|
|
|
|
- ulong32 powerstate;
|
|
|
|
- ulong32 wake_linkstatus;
|
|
|
|
- ulong32 wake_magicpacket;
|
|
|
|
- ulong32 wake_framepattern;
|
|
|
|
- inicpm_wakepattern_t wakepattern[SLIC_PM_MAXPATTERNS];
|
|
|
|
-} inicpm_state_t, *p_inicpm_state_t;
|
|
|
|
-
|
|
|
|
-typedef struct _slicpm_packet_pattern {
|
|
|
|
- ulong32 priority;
|
|
|
|
- ulong32 reserved;
|
|
|
|
- ulong32 masksize;
|
|
|
|
- ulong32 patternoffset;
|
|
|
|
- ulong32 patternsize;
|
|
|
|
- ulong32 patternflags;
|
|
|
|
-} slicpm_packet_pattern_t, *p_slicpm_packet_pattern_t;
|
|
|
|
-
|
|
|
|
-typedef enum _slicpm_power_state {
|
|
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct inicpm_wakepattern {
|
|
|
|
+ u32 patternlength;
|
|
|
|
+ unsigned char pattern[SLIC_PM_PATTERNSIZE];
|
|
|
|
+ unsigned char mask[SLIC_PM_PATTERNSIZE];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct inicpm_state {
|
|
|
|
+ u32 powercaps;
|
|
|
|
+ u32 powerstate;
|
|
|
|
+ u32 wake_linkstatus;
|
|
|
|
+ u32 wake_magicpacket;
|
|
|
|
+ u32 wake_framepattern;
|
|
|
|
+ struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct slicpm_packet_pattern {
|
|
|
|
+ u32 priority;
|
|
|
|
+ u32 reserved;
|
|
|
|
+ u32 masksize;
|
|
|
|
+ u32 patternoffset;
|
|
|
|
+ u32 patternsize;
|
|
|
|
+ u32 patternflags;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+enum slicpm_power_state {
|
|
slicpm_state_unspecified = 0,
|
|
slicpm_state_unspecified = 0,
|
|
slicpm_state_d0,
|
|
slicpm_state_d0,
|
|
slicpm_state_d1,
|
|
slicpm_state_d1,
|
|
slicpm_state_d2,
|
|
slicpm_state_d2,
|
|
slicpm_state_d3,
|
|
slicpm_state_d3,
|
|
slicpm_state_maximum
|
|
slicpm_state_maximum
|
|
-} slicpm_state_t, *p_slicpm_state_t;
|
|
|
|
-
|
|
|
|
-typedef struct _slicpm_wakeup_capabilities {
|
|
|
|
- slicpm_state_t min_magic_packet_wakeup;
|
|
|
|
- slicpm_state_t min_pattern_wakeup;
|
|
|
|
- slicpm_state_t min_link_change_wakeup;
|
|
|
|
-} slicpm_wakeup_capabilities_t, *p_slicpm_wakeup_capabilities_t;
|
|
|
|
-
|
|
|
|
-
|
|
|
|
-typedef struct _slic_pnp_capabilities {
|
|
|
|
- ulong32 flags;
|
|
|
|
- slicpm_wakeup_capabilities_t wakeup_capabilities;
|
|
|
|
-} slic_pnp_capabilities_t, *p_slic_pnp_capabilities_t;
|
|
|
|
-
|
|
|
|
-typedef struct _xmt_stats_t {
|
|
|
|
- ulong32 xmit_tcp_bytes;
|
|
|
|
- ulong32 xmit_tcp_segs;
|
|
|
|
- ulong32 xmit_bytes;
|
|
|
|
- ulong32 xmit_collisions;
|
|
|
|
- ulong32 xmit_unicasts;
|
|
|
|
- ulong32 xmit_other_error;
|
|
|
|
- ulong32 xmit_excess_collisions;
|
|
|
|
-} xmt_stats100_t;
|
|
|
|
-
|
|
|
|
-typedef struct _rcv_stats_t {
|
|
|
|
- ulong32 rcv_tcp_bytes;
|
|
|
|
- ulong32 rcv_tcp_segs;
|
|
|
|
- ulong32 rcv_bytes;
|
|
|
|
- ulong32 rcv_unicasts;
|
|
|
|
- ulong32 rcv_other_error;
|
|
|
|
- ulong32 rcv_drops;
|
|
|
|
-} rcv_stats100_t;
|
|
|
|
-
|
|
|
|
-typedef struct _xmt_statsgb_t {
|
|
|
|
- ulong64 xmit_tcp_bytes;
|
|
|
|
- ulong64 xmit_tcp_segs;
|
|
|
|
- ulong64 xmit_bytes;
|
|
|
|
- ulong64 xmit_collisions;
|
|
|
|
- ulong64 xmit_unicasts;
|
|
|
|
- ulong64 xmit_other_error;
|
|
|
|
- ulong64 xmit_excess_collisions;
|
|
|
|
-} xmt_statsGB_t;
|
|
|
|
-
|
|
|
|
-typedef struct _rcv_statsgb_t {
|
|
|
|
- ulong64 rcv_tcp_bytes;
|
|
|
|
- ulong64 rcv_tcp_segs;
|
|
|
|
- ulong64 rcv_bytes;
|
|
|
|
- ulong64 rcv_unicasts;
|
|
|
|
- u64 rcv_other_error;
|
|
|
|
- ulong64 rcv_drops;
|
|
|
|
-} rcv_statsGB_t;
|
|
|
|
-
|
|
|
|
-typedef struct _slic_stats {
|
|
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct slicpm_wakeup_capabilities {
|
|
|
|
+ enum slicpm_power_state min_magic_packet_wakeup;
|
|
|
|
+ enum slicpm_power_state min_pattern_wakeup;
|
|
|
|
+ enum slicpm_power_state min_link_change_wakeup;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct slic_pnp_capabilities {
|
|
|
|
+ u32 flags;
|
|
|
|
+ struct slicpm_wakeup_capabilities wakeup_capabilities;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct xmt_stats {
|
|
|
|
+ u32 xmit_tcp_bytes;
|
|
|
|
+ u32 xmit_tcp_segs;
|
|
|
|
+ u32 xmit_bytes;
|
|
|
|
+ u32 xmit_collisions;
|
|
|
|
+ u32 xmit_unicasts;
|
|
|
|
+ u32 xmit_other_error;
|
|
|
|
+ u32 xmit_excess_collisions;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct rcv_stats {
|
|
|
|
+ u32 rcv_tcp_bytes;
|
|
|
|
+ u32 rcv_tcp_segs;
|
|
|
|
+ u32 rcv_bytes;
|
|
|
|
+ u32 rcv_unicasts;
|
|
|
|
+ u32 rcv_other_error;
|
|
|
|
+ u32 rcv_drops;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct xmt_statsgb {
|
|
|
|
+ u64 xmit_tcp_bytes;
|
|
|
|
+ u64 xmit_tcp_segs;
|
|
|
|
+ u64 xmit_bytes;
|
|
|
|
+ u64 xmit_collisions;
|
|
|
|
+ u64 xmit_unicasts;
|
|
|
|
+ u64 xmit_other_error;
|
|
|
|
+ u64 xmit_excess_collisions;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct rcv_statsgb {
|
|
|
|
+ u64 rcv_tcp_bytes;
|
|
|
|
+ u64 rcv_tcp_segs;
|
|
|
|
+ u64 rcv_bytes;
|
|
|
|
+ u64 rcv_unicasts;
|
|
|
|
+ u64 rcv_other_error;
|
|
|
|
+ u64 rcv_drops;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct slic_stats {
|
|
union {
|
|
union {
|
|
struct {
|
|
struct {
|
|
- xmt_stats100_t xmt100;
|
|
|
|
- rcv_stats100_t rcv100;
|
|
|
|
|
|
+ struct xmt_stats xmt100;
|
|
|
|
+ struct rcv_stats rcv100;
|
|
} stats_100;
|
|
} stats_100;
|
|
struct {
|
|
struct {
|
|
- xmt_statsGB_t xmtGB;
|
|
|
|
- rcv_statsGB_t rcvGB;
|
|
|
|
|
|
+ struct xmt_statsgb xmtGB;
|
|
|
|
+ struct rcv_statsgb rcvGB;
|
|
} stats_GB;
|
|
} stats_GB;
|
|
} u;
|
|
} u;
|
|
-} slic_stats_t, *p_slic_stats_t;
|
|
|
|
|
|
+};
|
|
|
|
|
|
#define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs
|
|
#define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs
|
|
#define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes
|
|
#define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes
|
|
@@ -658,10 +652,9 @@ typedef struct _slic_stats {
|
|
#define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error
|
|
#define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error
|
|
#define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops
|
|
#define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops
|
|
|
|
|
|
-typedef struct _slic_config_mac_t {
|
|
|
|
- uchar macaddrA[6];
|
|
|
|
-
|
|
|
|
-} slic_config_mac_t, *pslic_config_mac_t;
|
|
|
|
|
|
+struct slic_config_mac {
|
|
|
|
+ unsigned char macaddrA[6];
|
|
|
|
+};
|
|
|
|
|
|
#define ATK_FRU_FORMAT 0x00
|
|
#define ATK_FRU_FORMAT 0x00
|
|
#define VENDOR1_FRU_FORMAT 0x01
|
|
#define VENDOR1_FRU_FORMAT 0x01
|
|
@@ -670,68 +663,68 @@ typedef struct _slic_config_mac_t {
|
|
#define VENDOR4_FRU_FORMAT 0x04
|
|
#define VENDOR4_FRU_FORMAT 0x04
|
|
#define NO_FRU_FORMAT 0xFF
|
|
#define NO_FRU_FORMAT 0xFF
|
|
|
|
|
|
-typedef struct _atk_fru_t {
|
|
|
|
- uchar assembly[6];
|
|
|
|
- uchar revision[2];
|
|
|
|
- uchar serial[14];
|
|
|
|
- uchar pad[3];
|
|
|
|
-} atk_fru_t, *patk_fru_t;
|
|
|
|
-
|
|
|
|
-typedef struct _vendor1_fru_t {
|
|
|
|
- uchar commodity;
|
|
|
|
- uchar assembly[4];
|
|
|
|
- uchar revision[2];
|
|
|
|
- uchar supplier[2];
|
|
|
|
- uchar date[2];
|
|
|
|
- uchar sequence[3];
|
|
|
|
- uchar pad[13];
|
|
|
|
-} vendor1_fru_t, *pvendor1_fru_t;
|
|
|
|
-
|
|
|
|
-typedef struct _vendor2_fru_t {
|
|
|
|
- uchar part[8];
|
|
|
|
- uchar supplier[5];
|
|
|
|
- uchar date[3];
|
|
|
|
- uchar sequence[4];
|
|
|
|
- uchar pad[7];
|
|
|
|
-} vendor2_fru_t, *pvendor2_fru_t;
|
|
|
|
-
|
|
|
|
-typedef struct _vendor3_fru_t {
|
|
|
|
- uchar assembly[6];
|
|
|
|
- uchar revision[2];
|
|
|
|
- uchar serial[14];
|
|
|
|
- uchar pad[3];
|
|
|
|
-} vendor3_fru_t, *pvendor3_fru_t;
|
|
|
|
-
|
|
|
|
-typedef struct _vendor4_fru_t {
|
|
|
|
- uchar number[8];
|
|
|
|
- uchar part[8];
|
|
|
|
- uchar version[8];
|
|
|
|
- uchar pad[3];
|
|
|
|
-} vendor4_fru_t, *pvendor4_fru_t;
|
|
|
|
-
|
|
|
|
-typedef union _oemfru_t {
|
|
|
|
- vendor1_fru_t vendor1_fru;
|
|
|
|
- vendor2_fru_t vendor2_fru;
|
|
|
|
- vendor3_fru_t vendor3_fru;
|
|
|
|
- vendor4_fru_t vendor4_fru;
|
|
|
|
-} oemfru_t, *poemfru_t;
|
|
|
|
|
|
+struct atk_fru {
|
|
|
|
+ unsigned char assembly[6];
|
|
|
|
+ unsigned char revision[2];
|
|
|
|
+ unsigned char serial[14];
|
|
|
|
+ unsigned char pad[3];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct vendor1_fru {
|
|
|
|
+ unsigned char commodity;
|
|
|
|
+ unsigned char assembly[4];
|
|
|
|
+ unsigned char revision[2];
|
|
|
|
+ unsigned char supplier[2];
|
|
|
|
+ unsigned char date[2];
|
|
|
|
+ unsigned char sequence[3];
|
|
|
|
+ unsigned char pad[13];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct vendor2_fru {
|
|
|
|
+ unsigned char part[8];
|
|
|
|
+ unsigned char supplier[5];
|
|
|
|
+ unsigned char date[3];
|
|
|
|
+ unsigned char sequence[4];
|
|
|
|
+ unsigned char pad[7];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct vendor3_fru {
|
|
|
|
+ unsigned char assembly[6];
|
|
|
|
+ unsigned char revision[2];
|
|
|
|
+ unsigned char serial[14];
|
|
|
|
+ unsigned char pad[3];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct vendor4_fru {
|
|
|
|
+ unsigned char number[8];
|
|
|
|
+ unsigned char part[8];
|
|
|
|
+ unsigned char version[8];
|
|
|
|
+ unsigned char pad[3];
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+union oemfru_t {
|
|
|
|
+ struct vendor1_fru vendor1_fru;
|
|
|
|
+ struct vendor2_fru vendor2_fru;
|
|
|
|
+ struct vendor3_fru vendor3_fru;
|
|
|
|
+ struct vendor4_fru vendor4_fru;
|
|
|
|
+};
|
|
|
|
|
|
/*
|
|
/*
|
|
SLIC EEPROM structure for Mojave
|
|
SLIC EEPROM structure for Mojave
|
|
*/
|
|
*/
|
|
-typedef struct _slic_eeprom {
|
|
|
|
|
|
+struct slic_eeprom {
|
|
ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
|
|
ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
|
|
ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
|
|
ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
|
|
ushort FlashSize; /* 02 Flash size */
|
|
ushort FlashSize; /* 02 Flash size */
|
|
ushort EepromSize; /* 03 EEPROM Size */
|
|
ushort EepromSize; /* 03 EEPROM Size */
|
|
ushort VendorId; /* 04 Vendor ID */
|
|
ushort VendorId; /* 04 Vendor ID */
|
|
ushort DeviceId; /* 05 Device ID */
|
|
ushort DeviceId; /* 05 Device ID */
|
|
- uchar RevisionId; /* 06 Revision ID */
|
|
|
|
- uchar ClassCode[3]; /* 07 Class Code */
|
|
|
|
- uchar DbgIntPin; /* 08 Debug Interrupt pin */
|
|
|
|
- uchar NetIntPin0; /* Network Interrupt Pin */
|
|
|
|
- uchar MinGrant; /* 09 Minimum grant */
|
|
|
|
- uchar MaxLat; /* Maximum Latency */
|
|
|
|
|
|
+ unsigned char RevisionId; /* 06 Revision ID */
|
|
|
|
+ unsigned char ClassCode[3]; /* 07 Class Code */
|
|
|
|
+ unsigned char DbgIntPin; /* 08 Debug Interrupt pin */
|
|
|
|
+ unsigned char NetIntPin0; /* Network Interrupt Pin */
|
|
|
|
+ unsigned char MinGrant; /* 09 Minimum grant */
|
|
|
|
+ unsigned char MaxLat; /* Maximum Latency */
|
|
ushort PciStatus; /* 10 PCI Status */
|
|
ushort PciStatus; /* 10 PCI Status */
|
|
ushort SubSysVId; /* 11 Subsystem Vendor Id */
|
|
ushort SubSysVId; /* 11 Subsystem Vendor Id */
|
|
ushort SubSysId; /* 12 Subsystem ID */
|
|
ushort SubSysId; /* 12 Subsystem ID */
|
|
@@ -739,58 +732,60 @@ typedef struct _slic_eeprom {
|
|
ushort DramRomFn; /* 14 Dram/Rom function */
|
|
ushort DramRomFn; /* 14 Dram/Rom function */
|
|
ushort DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
|
|
ushort DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
|
|
ushort RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
|
|
ushort RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
|
|
- uchar NetIntPin1; /* 17 Network Interface Pin 1 (simba/leone only) */
|
|
|
|
- uchar NetIntPin2; /* Network Interface Pin 2 (simba/leone only) */
|
|
|
|
|
|
+ unsigned char NetIntPin1;/* 17 Network Interface Pin 1
|
|
|
|
+ (simba/leone only) */
|
|
|
|
+ unsigned char NetIntPin2; /*Network Interface Pin 2 (simba/leone only)*/
|
|
union {
|
|
union {
|
|
- uchar NetIntPin3;/* 18 Network Interface Pin 3 (simba only) */
|
|
|
|
- uchar FreeTime;/* FreeTime setting (leone/mojave only) */
|
|
|
|
|
|
+ unsigned char NetIntPin3;/*18 Network Interface Pin 3
|
|
|
|
+ (simba only)*/
|
|
|
|
+ unsigned char FreeTime;/*FreeTime setting (leone/mojave only) */
|
|
} u1;
|
|
} u1;
|
|
- uchar TBIctl; /* 10-bit interface control (Mojave only) */
|
|
|
|
|
|
+ unsigned char TBIctl; /* 10-bit interface control (Mojave only) */
|
|
ushort DramSize; /* 19 DRAM size (bytes * 64k) */
|
|
ushort DramSize; /* 19 DRAM size (bytes * 64k) */
|
|
union {
|
|
union {
|
|
struct {
|
|
struct {
|
|
/* Mac Interface Specific portions */
|
|
/* Mac Interface Specific portions */
|
|
- slic_config_mac_t MacInfo[SLIC_NBR_MACS];
|
|
|
|
|
|
+ struct slic_config_mac MacInfo[SLIC_NBR_MACS];
|
|
} mac; /* MAC access for all boards */
|
|
} mac; /* MAC access for all boards */
|
|
struct {
|
|
struct {
|
|
/* use above struct for MAC access */
|
|
/* use above struct for MAC access */
|
|
- slic_config_mac_t pad[SLIC_NBR_MACS - 1];
|
|
|
|
|
|
+ struct slic_config_mac pad[SLIC_NBR_MACS - 1];
|
|
ushort DeviceId2; /* Device ID for 2nd
|
|
ushort DeviceId2; /* Device ID for 2nd
|
|
PCI function */
|
|
PCI function */
|
|
- uchar IntPin2; /* Interrupt pin for
|
|
|
|
|
|
+ unsigned char IntPin2; /* Interrupt pin for
|
|
2nd PCI function */
|
|
2nd PCI function */
|
|
- uchar ClassCode2[3]; /* Class Code for 2nd
|
|
|
|
|
|
+ unsigned char ClassCode2[3]; /* Class Code for 2nd
|
|
PCI function */
|
|
PCI function */
|
|
} mojave; /* 2nd function access for gigabit board */
|
|
} mojave; /* 2nd function access for gigabit board */
|
|
} u2;
|
|
} u2;
|
|
ushort CfgByte6; /* Config Byte 6 */
|
|
ushort CfgByte6; /* Config Byte 6 */
|
|
ushort PMECapab; /* Power Mgment capabilities */
|
|
ushort PMECapab; /* Power Mgment capabilities */
|
|
ushort NwClkCtrls; /* NetworkClockControls */
|
|
ushort NwClkCtrls; /* NetworkClockControls */
|
|
- uchar FruFormat; /* Alacritech FRU format type */
|
|
|
|
- atk_fru_t AtkFru; /* Alacritech FRU information */
|
|
|
|
- uchar OemFruFormat; /* optional OEM FRU format type */
|
|
|
|
- oemfru_t OemFru; /* optional OEM FRU information */
|
|
|
|
- uchar Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
|
|
|
|
|
|
+ unsigned char FruFormat; /* Alacritech FRU format type */
|
|
|
|
+ struct atk_fru AtkFru; /* Alacritech FRU information */
|
|
|
|
+ unsigned char OemFruFormat; /* optional OEM FRU format type */
|
|
|
|
+ union oemfru_t OemFru; /* optional OEM FRU information */
|
|
|
|
+ unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
|
|
*(if OEM FRU info exists) and two unusable
|
|
*(if OEM FRU info exists) and two unusable
|
|
* bytes at the end */
|
|
* bytes at the end */
|
|
-} slic_eeprom_t, *pslic_eeprom_t;
|
|
|
|
|
|
+};
|
|
|
|
|
|
/* SLIC EEPROM structure for Oasis */
|
|
/* SLIC EEPROM structure for Oasis */
|
|
-typedef struct _oslic_eeprom_t {
|
|
|
|
|
|
+struct oslic_eeprom {
|
|
ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
|
|
ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
|
|
ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
|
|
ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
|
|
ushort FlashConfig0; /* 02 Flash Config for SPI device 0 */
|
|
ushort FlashConfig0; /* 02 Flash Config for SPI device 0 */
|
|
ushort FlashConfig1; /* 03 Flash Config for SPI device 1 */
|
|
ushort FlashConfig1; /* 03 Flash Config for SPI device 1 */
|
|
ushort VendorId; /* 04 Vendor ID */
|
|
ushort VendorId; /* 04 Vendor ID */
|
|
ushort DeviceId; /* 05 Device ID (function 0) */
|
|
ushort DeviceId; /* 05 Device ID (function 0) */
|
|
- uchar RevisionId; /* 06 Revision ID */
|
|
|
|
- uchar ClassCode[3]; /* 07 Class Code for PCI function 0 */
|
|
|
|
- uchar IntPin1; /* 08 Interrupt pin for PCI function 1*/
|
|
|
|
- uchar ClassCode2[3]; /* 09 Class Code for PCI function 1 */
|
|
|
|
- uchar IntPin2; /* 10 Interrupt pin for PCI function 2*/
|
|
|
|
- uchar IntPin0; /* Interrupt pin for PCI function 0*/
|
|
|
|
- uchar MinGrant; /* 11 Minimum grant */
|
|
|
|
- uchar MaxLat; /* Maximum Latency */
|
|
|
|
|
|
+ unsigned char RevisionId; /* 06 Revision ID */
|
|
|
|
+ unsigned char ClassCode[3]; /* 07 Class Code for PCI function 0 */
|
|
|
|
+ unsigned char IntPin1; /* 08 Interrupt pin for PCI function 1*/
|
|
|
|
+ unsigned char ClassCode2[3]; /* 09 Class Code for PCI function 1 */
|
|
|
|
+ unsigned char IntPin2; /* 10 Interrupt pin for PCI function 2*/
|
|
|
|
+ unsigned char IntPin0; /* Interrupt pin for PCI function 0*/
|
|
|
|
+ unsigned char MinGrant; /* 11 Minimum grant */
|
|
|
|
+ unsigned char MaxLat; /* Maximum Latency */
|
|
ushort SubSysVId; /* 12 Subsystem Vendor Id */
|
|
ushort SubSysVId; /* 12 Subsystem Vendor Id */
|
|
ushort SubSysId; /* 13 Subsystem ID */
|
|
ushort SubSysId; /* 13 Subsystem ID */
|
|
ushort FlashSize; /* 14 Flash size (bytes / 4K) */
|
|
ushort FlashSize; /* 14 Flash size (bytes / 4K) */
|
|
@@ -801,8 +796,8 @@ typedef struct _oslic_eeprom_t {
|
|
ushort DeviceId2; /* 18 Device Id (function 2) */
|
|
ushort DeviceId2; /* 18 Device Id (function 2) */
|
|
ushort CfgByte6; /* 19 Device Status Config Bytes 6-7 */
|
|
ushort CfgByte6; /* 19 Device Status Config Bytes 6-7 */
|
|
ushort PMECapab; /* 20 Power Mgment capabilities */
|
|
ushort PMECapab; /* 20 Power Mgment capabilities */
|
|
- uchar MSICapab; /* 21 MSI capabilities */
|
|
|
|
- uchar ClockDivider; /* Clock divider */
|
|
|
|
|
|
+ unsigned char MSICapab; /* 21 MSI capabilities */
|
|
|
|
+ unsigned char ClockDivider; /* Clock divider */
|
|
ushort PciStatusLow; /* 22 PCI Status bits 15:0 */
|
|
ushort PciStatusLow; /* 22 PCI Status bits 15:0 */
|
|
ushort PciStatusHigh; /* 23 PCI Status bits 31:16 */
|
|
ushort PciStatusHigh; /* 23 PCI Status bits 31:16 */
|
|
ushort DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
|
|
ushort DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
|
|
@@ -810,18 +805,18 @@ typedef struct _oslic_eeprom_t {
|
|
ushort DramSize; /* 26 DRAM size (bytes / 64K) */
|
|
ushort DramSize; /* 26 DRAM size (bytes / 64K) */
|
|
ushort GpioTbiCtl;/* 27 GPIO/TBI controls for functions 1/0 */
|
|
ushort GpioTbiCtl;/* 27 GPIO/TBI controls for functions 1/0 */
|
|
ushort EepromSize; /* 28 EEPROM Size */
|
|
ushort EepromSize; /* 28 EEPROM Size */
|
|
- slic_config_mac_t MacInfo[2]; /* 29 MAC addresses (2 ports) */
|
|
|
|
- uchar FruFormat; /* 35 Alacritech FRU format type */
|
|
|
|
- atk_fru_t AtkFru; /* Alacritech FRU information */
|
|
|
|
- uchar OemFruFormat; /* optional OEM FRU format type */
|
|
|
|
- oemfru_t OemFru; /* optional OEM FRU information */
|
|
|
|
- uchar Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
|
|
|
|
|
|
+ struct slic_config_mac MacInfo[2]; /* 29 MAC addresses (2 ports) */
|
|
|
|
+ unsigned char FruFormat; /* 35 Alacritech FRU format type */
|
|
|
|
+ struct atk_fru AtkFru; /* Alacritech FRU information */
|
|
|
|
+ unsigned char OemFruFormat; /* optional OEM FRU format type */
|
|
|
|
+ union oemfru_t OemFru; /* optional OEM FRU information */
|
|
|
|
+ unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
|
|
* (if OEM FRU info exists) and two unusable
|
|
* (if OEM FRU info exists) and two unusable
|
|
* bytes at the end
|
|
* bytes at the end
|
|
*/
|
|
*/
|
|
-} oslic_eeprom_t, *poslic_eeprom_t;
|
|
|
|
|
|
+};
|
|
|
|
|
|
-#define MAX_EECODE_SIZE sizeof(slic_eeprom_t)
|
|
|
|
|
|
+#define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
|
|
#define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
|
|
#define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
|
|
|
|
|
|
/* SLIC CONFIG structure
|
|
/* SLIC CONFIG structure
|
|
@@ -830,20 +825,20 @@ typedef struct _oslic_eeprom_t {
|
|
board types. It is filled in from the appropriate EEPROM structure
|
|
board types. It is filled in from the appropriate EEPROM structure
|
|
by SlicGetConfigData().
|
|
by SlicGetConfigData().
|
|
*/
|
|
*/
|
|
-typedef struct _slic_config_t {
|
|
|
|
- boolean EepromValid; /* Valid EEPROM flag (checksum good?) */
|
|
|
|
|
|
+struct slic_config {
|
|
|
|
+ bool EepromValid; /* Valid EEPROM flag (checksum good?) */
|
|
ushort DramSize; /* DRAM size (bytes / 64K) */
|
|
ushort DramSize; /* DRAM size (bytes / 64K) */
|
|
- slic_config_mac_t MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
|
|
|
|
- uchar FruFormat; /* Alacritech FRU format type */
|
|
|
|
- atk_fru_t AtkFru; /* Alacritech FRU information */
|
|
|
|
- uchar OemFruFormat; /* optional OEM FRU format type */
|
|
|
|
- union {
|
|
|
|
- vendor1_fru_t vendor1_fru;
|
|
|
|
- vendor2_fru_t vendor2_fru;
|
|
|
|
- vendor3_fru_t vendor3_fru;
|
|
|
|
- vendor4_fru_t vendor4_fru;
|
|
|
|
- } OemFru;
|
|
|
|
-} slic_config_t, *pslic_config_t;
|
|
|
|
|
|
+ struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
|
|
|
|
+ unsigned char FruFormat; /* Alacritech FRU format type */
|
|
|
|
+ struct atk_fru AtkFru; /* Alacritech FRU information */
|
|
|
|
+ unsigned char OemFruFormat; /* optional OEM FRU format type */
|
|
|
|
+ union {
|
|
|
|
+ struct vendor1_fru vendor1_fru;
|
|
|
|
+ struct vendor2_fru vendor2_fru;
|
|
|
|
+ struct vendor3_fru vendor3_fru;
|
|
|
|
+ struct vendor4_fru vendor4_fru;
|
|
|
|
+ } OemFru;
|
|
|
|
+};
|
|
|
|
|
|
#pragma pack()
|
|
#pragma pack()
|
|
|
|
|