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@@ -2528,50 +2528,6 @@ static void r100_errata(struct radeon_device *rdev)
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}
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}
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-/* Wait for vertical sync on primary CRTC */
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-static void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
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-{
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- uint32_t crtc_gen_cntl, tmp;
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- int i;
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-
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- crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
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- if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
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- !(crtc_gen_cntl & RADEON_CRTC_EN)) {
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- return;
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- }
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- /* Clear the CRTC_VBLANK_SAVE bit */
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- WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
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- for (i = 0; i < rdev->usec_timeout; i++) {
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- tmp = RREG32(RADEON_CRTC_STATUS);
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- if (tmp & RADEON_CRTC_VBLANK_SAVE) {
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- return;
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- }
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- DRM_UDELAY(1);
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- }
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-}
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-
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-/* Wait for vertical sync on secondary CRTC */
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-static void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
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-{
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- uint32_t crtc2_gen_cntl, tmp;
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- int i;
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-
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- crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
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- if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
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- !(crtc2_gen_cntl & RADEON_CRTC2_EN))
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- return;
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-
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- /* Clear the CRTC_VBLANK_SAVE bit */
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- WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
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- for (i = 0; i < rdev->usec_timeout; i++) {
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- tmp = RREG32(RADEON_CRTC2_STATUS);
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- if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
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- return;
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- }
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- DRM_UDELAY(1);
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- }
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-}
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-
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static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
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{
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unsigned i;
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