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@@ -94,27 +94,30 @@
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* these need to be ordered in number of appearance in the
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* these need to be ordered in number of appearance in the
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* SUBSRC mask register
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* SUBSRC mask register
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*/
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*/
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-#define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */
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-#define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */
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-#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
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-#define IRQ_S3CUART_RX1 S3C2410_IRQ(57)
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-#define IRQ_S3CUART_TX1 S3C2410_IRQ(58)
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-#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
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+#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54)
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-#define IRQ_S3CUART_RX2 S3C2410_IRQ(60)
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-#define IRQ_S3CUART_TX2 S3C2410_IRQ(61)
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-#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
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+#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */
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+#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
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+#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
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-#define IRQ_TC S3C2410_IRQ(63)
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-#define IRQ_ADC S3C2410_IRQ(64)
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+#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */
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+#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
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+#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
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+
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+#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */
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+#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
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+#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
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+
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+#define IRQ_TC S3C2410_IRQSUB(9)
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+#define IRQ_ADC S3C2410_IRQSUB(10)
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/* extra irqs for s3c2440 */
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/* extra irqs for s3c2440 */
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-#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65)
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-#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66)
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-#define IRQ_S3C2440_WDT S3C2410_IRQ(67)
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-#define IRQ_S3C2440_AC97 S3C2410_IRQ(68)
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+#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11)
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+#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12)
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+#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
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+#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
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#define NR_IRQS (IRQ_S3C2440_AC97+1)
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#define NR_IRQS (IRQ_S3C2440_AC97+1)
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