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@@ -21,8 +21,8 @@
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#include "reg.h"
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#include "dcr.h"
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-/* Read the 44x memory controller to get size of system memory. */
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-void ibm44x_fixup_memsize(void)
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+/* Read the 4xx SDRAM controller to get size of system memory. */
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+void ibm4xx_fixup_memsize(void)
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{
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int i;
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unsigned long memsize, bank_config;
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@@ -39,8 +39,9 @@ void ibm44x_fixup_memsize(void)
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dt_fixup_memory(0, memsize);
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}
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-#define SPRN_DBCR0 0x134
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-#define DBCR0_RST_SYSTEM 0x30000000
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+#define SPRN_DBCR0_40X 0x3F2
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+#define SPRN_DBCR0_44X 0x134
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+#define DBCR0_RST_SYSTEM 0x30000000
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void ibm44x_dbcr_reset(void)
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{
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@@ -50,11 +51,35 @@ void ibm44x_dbcr_reset(void)
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"mfspr %0,%1\n"
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"oris %0,%0,%2@h\n"
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"mtspr %1,%0"
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- : "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM)
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+ : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
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);
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}
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+void ibm40x_dbcr_reset(void)
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+{
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+ unsigned long tmp;
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+
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+ asm volatile (
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+ "mfspr %0,%1\n"
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+ "oris %0,%0,%2@h\n"
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+ "mtspr %1,%0"
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+ : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
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+ );
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+}
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+
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+#define EMAC_RESET 0x20000000
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+void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
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+{
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+ /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
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+ if (emac0)
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+ *emac0 = EMAC_RESET;
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+ if (emac1)
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+ *emac1 = EMAC_RESET;
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+
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+ mtdcr(DCRN_MAL0_CFG, MAL_RESET);
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+}
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+
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/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
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* banks into the OPB address space */
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void ibm4xx_fixup_ebc_ranges(const char *ebc)
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