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@@ -395,3 +395,49 @@ void wl1271_reg_write32(struct wl1271 *wl, int addr, u32 val)
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{
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wl1271_write32(wl, wl1271_translate_addr(wl, addr), val);
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}
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+
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+void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
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+{
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+ /* write address >> 1 + 0x30000 to OCP_POR_CTR */
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+ addr = (addr >> 1) + 0x30000;
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+ wl1271_reg_write32(wl, OCP_POR_CTR, addr);
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+
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+ /* write value to OCP_POR_WDATA */
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+ wl1271_reg_write32(wl, OCP_DATA_WRITE, val);
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+
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+ /* write 1 to OCP_CMD */
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+ wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_WRITE);
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+}
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+
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+u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
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+{
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+ u32 val;
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+ int timeout = OCP_CMD_LOOP;
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+
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+ /* write address >> 1 + 0x30000 to OCP_POR_CTR */
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+ addr = (addr >> 1) + 0x30000;
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+ wl1271_reg_write32(wl, OCP_POR_CTR, addr);
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+
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+ /* write 2 to OCP_CMD */
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+ wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_READ);
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+
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+ /* poll for data ready */
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+ do {
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+ val = wl1271_reg_read32(wl, OCP_DATA_READ);
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+ timeout--;
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+ } while (!(val & OCP_READY_MASK) && timeout);
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+
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+ if (!timeout) {
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+ wl1271_warning("Top register access timed out.");
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+ return 0xffff;
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+ }
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+
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+ /* check data status and return if OK */
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+ if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
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+ return val & 0xffff;
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+ else {
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+ wl1271_warning("Top register access returned error.");
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+ return 0xffff;
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+ }
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+}
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+
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