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@@ -1334,10 +1334,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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u32 reg;
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uint32_t DP = intel_dp->DP;
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- /* Enable output, wait for it to become active */
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- I915_WRITE(intel_dp->output_reg, intel_dp->DP);
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- POSTING_READ(intel_dp->output_reg);
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- intel_wait_for_vblank(dev, intel_crtc->pipe);
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+ /*
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+ * On CPT we have to enable the port in training pattern 1, which
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+ * will happen below in intel_dp_set_link_train. Otherwise, enable
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+ * the port and wait for it to become active.
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+ */
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+ if (!HAS_PCH_CPT(dev)) {
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+ I915_WRITE(intel_dp->output_reg, intel_dp->DP);
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+ POSTING_READ(intel_dp->output_reg);
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+ intel_wait_for_vblank(dev, intel_crtc->pipe);
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+ }
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/* Write the link configuration data */
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intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
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