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@@ -818,7 +818,7 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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- u32 regval;
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+ u32 regval, i;
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ath_dbg(common, MCI, "MCI Reset (full_sleep = %d, is_2g = %d)\n",
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is_full_sleep, is_2g);
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@@ -868,6 +868,18 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 1);
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REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
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+ /* concurrent tx priority */
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+ if (mci->config & ATH_MCI_CONFIG_CONCUR_TX) {
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+ REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
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+ AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE, 0);
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+ REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
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+ AR_BTCOEX_CTRL2_TXPWR_THRESH, 0x7f);
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+ REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
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+ AR_BTCOEX_CTRL_REDUCE_TXPWR, 0);
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+ for (i = 0; i < 8; i++)
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+ REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), 0x7f7f7f7f);
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+ }
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+
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regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV);
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REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
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REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
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@@ -1426,3 +1438,17 @@ void ar9003_mci_send_wlan_channels(struct ath_hw *ah)
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ar9003_mci_send_coex_wlan_channels(ah, true);
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}
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EXPORT_SYMBOL(ar9003_mci_send_wlan_channels);
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+
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+u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode)
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+{
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+ if (!ah->btcoex_hw.mci.concur_tx)
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+ goto out;
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+
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+ if (ctlmode == CTL_2GHT20)
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+ return ATH_BTCOEX_HT20_MAX_TXPOWER;
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+ else if (ctlmode == CTL_2GHT40)
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+ return ATH_BTCOEX_HT40_MAX_TXPOWER;
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+
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+out:
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+ return -1;
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+}
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