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@@ -26,6 +26,7 @@
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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+#include <linux/delay.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/sh_timer.h>
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@@ -150,13 +151,13 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
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static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
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{
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- int ret;
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+ int k, ret;
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/* enable clock */
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ret = clk_enable(p->clk);
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if (ret) {
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dev_err(&p->pdev->dev, "cannot enable clock\n");
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- return ret;
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+ goto err0;
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}
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/* make sure channel is disabled */
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@@ -174,9 +175,38 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
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sh_cmt_write(p, CMCOR, 0xffffffff);
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sh_cmt_write(p, CMCNT, 0);
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+ /*
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+ * According to the sh73a0 user's manual, as CMCNT can be operated
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+ * only by the RCLK (Pseudo 32 KHz), there's one restriction on
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+ * modifying CMCNT register; two RCLK cycles are necessary before
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+ * this register is either read or any modification of the value
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+ * it holds is reflected in the LSI's actual operation.
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+ *
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+ * While at it, we're supposed to clear out the CMCNT as of this
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+ * moment, so make sure it's processed properly here. This will
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+ * take RCLKx2 at maximum.
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+ */
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+ for (k = 0; k < 100; k++) {
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+ if (!sh_cmt_read(p, CMCNT))
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+ break;
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+ udelay(1);
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+ }
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+
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+ if (sh_cmt_read(p, CMCNT)) {
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+ dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
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+ ret = -ETIMEDOUT;
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+ goto err1;
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+ }
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+
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/* enable channel */
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sh_cmt_start_stop_ch(p, 1);
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return 0;
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+ err1:
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+ /* stop clock */
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+ clk_disable(p->clk);
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+
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+ err0:
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+ return ret;
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}
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static void sh_cmt_disable(struct sh_cmt_priv *p)
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