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@@ -779,7 +779,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
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rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
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rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
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rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
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rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
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rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
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rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
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- rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
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+ rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
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rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
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rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
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rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
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rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
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@@ -795,13 +795,13 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
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entry_priv->desc_dma);
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entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
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rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
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- entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
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+ entry_priv = rt2x00dev->atim->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
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rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
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entry_priv->desc_dma);
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entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
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rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
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- entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
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+ entry_priv = rt2x00dev->bcn->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
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rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
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entry_priv->desc_dma);
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entry_priv->desc_dma);
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