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x86: add clflush before monitor for Intel 7400 series

For Intel 7400 series CPUs, the recommendation is to use a clflush on the
monitored address just before monitor and mwait pair [1].

This clflush makes sure that there are no false wakeups from mwait when the
monitored address was recently written to.

[1] "MONITOR/MWAIT Recommendations for Intel Xeon Processor 7400 series"
    section in specification update document of 7400 series
    http://download.intel.com/design/xeon/specupdt/32033601.pdf

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Pallipadi, Venkatesh 16 years ago
parent
commit
e736ad548d
3 changed files with 10 additions and 0 deletions
  1. 1 0
      arch/x86/include/asm/cpufeature.h
  2. 3 0
      arch/x86/kernel/cpu/intel.c
  3. 6 0
      arch/x86/kernel/process.c

+ 1 - 0
arch/x86/include/asm/cpufeature.h

@@ -93,6 +93,7 @@
 #define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
 #define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
+#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
 
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
 #define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */

+ 3 - 0
arch/x86/kernel/cpu/intel.c

@@ -291,6 +291,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 		ds_init_intel(c);
 		ds_init_intel(c);
 	}
 	}
 
 
+	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
+		set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
+
 #ifdef CONFIG_X86_64
 #ifdef CONFIG_X86_64
 	if (c->x86 == 15)
 	if (c->x86 == 15)
 		c->x86_cache_alignment = c->x86_clflush_size * 2;
 		c->x86_cache_alignment = c->x86_clflush_size * 2;

+ 6 - 0
arch/x86/kernel/process.c

@@ -180,6 +180,9 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 
 
 	trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 	trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 	if (!need_resched()) {
 	if (!need_resched()) {
+		if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
+			clflush((void *)&current_thread_info()->flags);
+
 		__monitor((void *)&current_thread_info()->flags, 0, 0);
 		__monitor((void *)&current_thread_info()->flags, 0, 0);
 		smp_mb();
 		smp_mb();
 		if (!need_resched())
 		if (!need_resched())
@@ -194,6 +197,9 @@ static void mwait_idle(void)
 	struct power_trace it;
 	struct power_trace it;
 	if (!need_resched()) {
 	if (!need_resched()) {
 		trace_power_start(&it, POWER_CSTATE, 1);
 		trace_power_start(&it, POWER_CSTATE, 1);
+		if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
+			clflush((void *)&current_thread_info()->flags);
+
 		__monitor((void *)&current_thread_info()->flags, 0, 0);
 		__monitor((void *)&current_thread_info()->flags, 0, 0);
 		smp_mb();
 		smp_mb();
 		if (!need_resched())
 		if (!need_resched())