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@@ -6226,6 +6226,8 @@ static int tg3_chip_reset(struct tg3 *tp)
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udelay(120);
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if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
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+ u16 val16;
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+
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if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
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int i;
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u32 cfg_val;
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@@ -6239,12 +6241,22 @@ static int tg3_chip_reset(struct tg3 *tp)
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cfg_val | (1 << 15));
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}
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- /* Set PCIE max payload size to 128 bytes and
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- * clear the "no snoop" and "relaxed ordering" bits.
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+ /* Clear the "no snoop" and "relaxed ordering" bits. */
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+ pci_read_config_word(tp->pdev,
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+ tp->pcie_cap + PCI_EXP_DEVCTL,
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+ &val16);
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+ val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
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+ PCI_EXP_DEVCTL_NOSNOOP_EN);
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+ /*
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+ * Older PCIe devices only support the 128 byte
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+ * MPS setting. Enforce the restriction.
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*/
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+ if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
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+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
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+ val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
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pci_write_config_word(tp->pdev,
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tp->pcie_cap + PCI_EXP_DEVCTL,
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- 0);
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+ val16);
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pcie_set_readrq(tp->pdev, 4096);
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