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@@ -340,7 +340,7 @@ int dmar_disabled = 0;
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int dmar_disabled = 1;
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#endif /*CONFIG_DMAR_DEFAULT_ON*/
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-static int __initdata dmar_map_gfx = 1;
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+static int dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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@@ -1874,14 +1874,15 @@ static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
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}
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}
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if (found) {
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+ spin_unlock_irqrestore(&device_domain_lock, flags);
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free_devinfo_mem(info);
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domain_exit(domain);
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domain = found;
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} else {
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list_add(&info->link, &domain->devices);
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list_add(&info->global, &device_domain_list);
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+ spin_unlock_irqrestore(&device_domain_lock, flags);
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}
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- spin_unlock_irqrestore(&device_domain_lock, flags);
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}
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found_domain:
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@@ -3603,7 +3604,8 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
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pte = dmar_domain->pgd;
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if (dma_pte_present(pte)) {
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free_pgtable_page(dmar_domain->pgd);
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- dmar_domain->pgd = (struct dma_pte *)dma_pte_addr(pte);
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+ dmar_domain->pgd = (struct dma_pte *)
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+ phys_to_virt(dma_pte_addr(pte));
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}
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dmar_domain->agaw--;
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}
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@@ -3719,6 +3721,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
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*/
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printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
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rwbf_quirk = 1;
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+
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+ /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
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+ if (dev->revision == 0x07) {
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+ printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
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+ dmar_map_gfx = 0;
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+ }
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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