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@@ -155,6 +155,7 @@ static DEFINE_SPINLOCK(microcode_update_lock);
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static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
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static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
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{
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu_num);
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struct cpuinfo_x86 *c = &cpu_data(cpu_num);
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+ unsigned long flags;
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unsigned int val[2];
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unsigned int val[2];
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memset(csig, 0, sizeof(*csig));
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memset(csig, 0, sizeof(*csig));
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@@ -174,11 +175,16 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
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csig->pf = 1 << ((val[1] >> 18) & 7);
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csig->pf = 1 << ((val[1] >> 18) & 7);
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}
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}
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+ /* serialize access to the physical write to MSR 0x79 */
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+ spin_lock_irqsave(µcode_update_lock, flags);
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+
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wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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/* see notes above for revision 1.07. Apparent chip bug */
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/* see notes above for revision 1.07. Apparent chip bug */
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sync_core();
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sync_core();
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/* get the current revision from MSR 0x8B */
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/* get the current revision from MSR 0x8B */
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rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
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rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
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+ spin_unlock_irqrestore(µcode_update_lock, flags);
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+
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pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
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pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
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csig->sig, csig->pf, csig->rev);
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csig->sig, csig->pf, csig->rev);
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