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@@ -44,23 +44,23 @@
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#define PMU_NONE(args)
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/* PLL controls/clocks */
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-static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc,
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+static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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u32 xtal);
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-static u32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
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-static u32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
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+static u32 si_pmu1_cpuclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc);
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+static u32 si_pmu1_alpclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc);
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/* PMU resources */
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static bool si_pmu_res_depfltr_bb(si_t *sih);
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static bool si_pmu_res_depfltr_ncb(si_t *sih);
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static bool si_pmu_res_depfltr_paldo(si_t *sih);
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static bool si_pmu_res_depfltr_npaldo(si_t *sih);
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-static u32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
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+static u32 si_pmu_res_deps(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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u32 rsrcs, bool all);
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-static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
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+static uint si_pmu_res_uptime(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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u8 rsrc);
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static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
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static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
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- osl_t *osh, u8 spuravoid);
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+ struct osl_info *osh, u8 spuravoid);
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static void si_pmu_set_4330_plldivs(si_t *sih);
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@@ -105,7 +105,7 @@ void si_pmu_pllupd(si_t *sih)
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}
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/* Setup switcher voltage */
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-void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, u8 bb_voltage,
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+void si_pmu_set_switcher_voltage(si_t *sih, struct osl_info *osh, u8 bb_voltage,
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u8 rf_voltage)
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{
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chipcregs_t *cc;
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@@ -128,7 +128,7 @@ void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, u8 bb_voltage,
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si_setcoreidx(sih, origidx);
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}
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-void si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, u8 ldo, u8 voltage)
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+void si_pmu_set_ldo_voltage(si_t *sih, struct osl_info *osh, u8 ldo, u8 voltage)
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{
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u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
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u8 addr = 0;
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@@ -186,7 +186,7 @@ void si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, u8 ldo, u8 voltage)
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/* d11 slow to fast clock transition time in slow clock cycles */
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#define D11SCC_SLOW2FAST_TRANSITION 2
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-u16 si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh)
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+u16 si_pmu_fast_pwrup_delay(si_t *sih, struct osl_info *osh)
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{
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uint delay = PMU_MAX_TRANSITION_DLY;
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chipcregs_t *cc;
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@@ -263,7 +263,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh)
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return (u16) delay;
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}
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-u32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force)
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+u32 si_pmu_force_ilp(si_t *sih, struct osl_info *osh, bool force)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -681,7 +681,7 @@ static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
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}
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/* initialize PMU resources */
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-void si_pmu_res_init(si_t *sih, osl_t *osh)
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+void si_pmu_res_init(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -1182,7 +1182,7 @@ static u32 si_pmu1_pllfvco0(si_t *sih)
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/* query alp/xtal clock frequency */
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static u32
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-si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc)
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+si_pmu1_alpclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc)
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{
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const pmu1_xtaltab0_t *xt;
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u32 xf;
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@@ -1207,7 +1207,8 @@ si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc)
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* case the xtal frequency is unknown to the s/w so we need to call
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* si_pmu1_xtaldef0() wherever it is needed to return a default value.
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*/
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-static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
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+static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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+ u32 xtal)
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{
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const pmu1_xtaltab0_t *xt;
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u32 tmp;
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@@ -1452,7 +1453,7 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
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/* query the CPU clock frequency */
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static u32
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-si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc)
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+si_pmu1_cpuclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc)
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{
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u32 tmp, m1div;
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#ifdef BCMDBG
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@@ -1506,7 +1507,7 @@ si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc)
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}
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/* initialize PLL */
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-void si_pmu_pll_init(si_t *sih, osl_t *osh, uint xtalfreq)
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+void si_pmu_pll_init(si_t *sih, struct osl_info *osh, uint xtalfreq)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -1559,7 +1560,7 @@ void si_pmu_pll_init(si_t *sih, osl_t *osh, uint xtalfreq)
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}
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/* query alp/xtal clock frequency */
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-u32 si_pmu_alp_clock(si_t *sih, osl_t *osh)
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+u32 si_pmu_alp_clock(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -1620,7 +1621,7 @@ u32 si_pmu_alp_clock(si_t *sih, osl_t *osh)
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* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
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*/
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static u32
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-si_pmu5_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
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+si_pmu5_clock(si_t *sih, struct osl_info *osh, chipcregs_t *cc, uint pll0,
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uint m) {
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u32 tmp, div, ndiv, p1, p2, fc;
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@@ -1673,7 +1674,7 @@ si_pmu5_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
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/* For designs that feed the same clock to both backplane
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* and CPU just return the CPU clock speed.
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*/
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-u32 si_pmu_si_clock(si_t *sih, osl_t *osh)
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+u32 si_pmu_si_clock(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -1752,7 +1753,7 @@ u32 si_pmu_si_clock(si_t *sih, osl_t *osh)
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}
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/* query CPU clock frequency */
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-u32 si_pmu_cpu_clock(si_t *sih, osl_t *osh)
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+u32 si_pmu_cpu_clock(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -1796,7 +1797,7 @@ u32 si_pmu_cpu_clock(si_t *sih, osl_t *osh)
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}
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/* query memory clock frequency */
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-u32 si_pmu_mem_clock(si_t *sih, osl_t *osh)
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+u32 si_pmu_mem_clock(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -1845,7 +1846,7 @@ u32 si_pmu_mem_clock(si_t *sih, osl_t *osh)
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static u32 ilpcycles_per_sec;
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-u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh)
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+u32 si_pmu_ilp_clock(si_t *sih, struct osl_info *osh)
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{
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if (ISSIM_ENAB(sih))
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return ILP_CLOCK;
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@@ -1909,7 +1910,7 @@ static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
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#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
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void
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-si_sdiod_drive_strength_init(si_t *sih, osl_t *osh,
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+si_sdiod_drive_strength_init(si_t *sih, struct osl_info *osh,
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u32 drivestrength) {
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chipcregs_t *cc;
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uint origidx, intr_val = 0;
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@@ -1980,7 +1981,7 @@ si_sdiod_drive_strength_init(si_t *sih, osl_t *osh,
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}
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/* initialize PMU */
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-void si_pmu_init(si_t *sih, osl_t *osh)
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+void si_pmu_init(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -2012,7 +2013,7 @@ void si_pmu_init(si_t *sih, osl_t *osh)
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/* Return up time in ILP cycles for the given resource. */
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static uint
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-si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
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+si_pmu_res_uptime(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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u8 rsrc) {
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u32 deps;
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uint up, i, dup, dmax;
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@@ -2049,7 +2050,7 @@ si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
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/* Return dependancies (direct or all/indirect) for the given resources */
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static u32
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-si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs,
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+si_pmu_res_deps(si_t *sih, struct osl_info *osh, chipcregs_t *cc, u32 rsrcs,
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bool all)
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{
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u32 deps = 0;
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@@ -2069,7 +2070,7 @@ si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs,
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}
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/* power up/down OTP through PMU resources */
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-void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
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+void si_pmu_otp_power(si_t *sih, struct osl_info *osh, bool on)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -2139,7 +2140,7 @@ void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
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si_setcoreidx(sih, origidx);
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}
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-void si_pmu_rcal(si_t *sih, osl_t *osh)
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+void si_pmu_rcal(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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@@ -2222,7 +2223,7 @@ void si_pmu_rcal(si_t *sih, osl_t *osh)
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si_setcoreidx(sih, origidx);
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}
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-void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid)
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+void si_pmu_spuravoid(si_t *sih, struct osl_info *osh, u8 spuravoid)
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{
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chipcregs_t *cc;
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uint origidx, intr_val;
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@@ -2259,7 +2260,7 @@ void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid)
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}
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static void
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-si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
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+si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, struct osl_info *osh,
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u8 spuravoid)
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{
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u32 tmp = 0;
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@@ -2455,7 +2456,7 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
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W_REG(osh, &cc->pmucontrol, tmp);
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}
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-bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
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+bool si_pmu_is_otp_powered(si_t *sih, struct osl_info *osh)
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{
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uint idx;
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chipcregs_t *cc;
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@@ -2507,9 +2508,9 @@ bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
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void
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#if defined(BCMDBG)
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-si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
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+si_pmu_sprom_enable(si_t *sih, struct osl_info *osh, bool enable)
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#else
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-si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
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+si_pmu_sprom_enable(si_t *sih, struct osl_info *osh, bool enable)
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#endif
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{
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chipcregs_t *cc;
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@@ -2525,7 +2526,7 @@ si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
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}
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/* initialize PMU chip controls and other chip level stuff */
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-void si_pmu_chip_init(si_t *sih, osl_t *osh)
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+void si_pmu_chip_init(si_t *sih, struct osl_info *osh)
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{
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uint origidx;
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@@ -2547,7 +2548,7 @@ void si_pmu_chip_init(si_t *sih, osl_t *osh)
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}
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/* initialize PMU switch/regulators */
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-void si_pmu_swreg_init(si_t *sih, osl_t *osh)
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+void si_pmu_swreg_init(si_t *sih, struct osl_info *osh)
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{
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ASSERT(sih->cccaps & CC_CAP_PMU);
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@@ -2591,7 +2592,7 @@ void si_pmu_radio_enable(si_t *sih, bool enable)
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/* Wait for a particular clock level to be on the backplane */
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u32
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-si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk,
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+si_pmu_waitforclk_on_backplane(si_t *sih, struct osl_info *osh, u32 clk,
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u32 delay)
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{
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chipcregs_t *cc;
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@@ -2620,7 +2621,7 @@ si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk,
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#define EXT_ILP_HZ 32768
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-u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh)
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+u32 si_pmu_measure_alpclk(si_t *sih, struct osl_info *osh)
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{
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chipcregs_t *cc;
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uint origidx;
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