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@@ -20,11 +20,12 @@
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#include <linux/kernel.h>
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#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock36xx.h"
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-
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+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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/**
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* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
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@@ -39,29 +40,28 @@
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*/
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int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
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{
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- struct clk_hw_omap *parent;
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+ struct clk_divider *parent;
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struct clk_hw *parent_hw;
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- u32 dummy_v, orig_v, clksel_shift;
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+ u32 dummy_v, orig_v;
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
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- parent = to_clk_hw_omap(parent_hw);
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+ parent = to_clk_divider(parent_hw);
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/* Restore the dividers */
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if (!ret) {
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- clksel_shift = __ffs(parent->clksel_mask);
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- orig_v = __raw_readl(parent->clksel_reg);
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+ orig_v = __raw_readl(parent->reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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- dummy_v ^= (1 << clksel_shift);
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- __raw_writel(dummy_v, parent->clksel_reg);
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+ dummy_v ^= (1 << parent->shift);
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+ __raw_writel(dummy_v, parent->reg);
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/* Write the original divider */
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- __raw_writel(orig_v, parent->clksel_reg);
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+ __raw_writel(orig_v, parent->reg);
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}
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return ret;
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