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@@ -23,9 +23,6 @@
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*
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* Integrator address map
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*
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- * NOTE: This is a multi-hosted header file for use with uHAL and
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- * supported debuggers.
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- *
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* ***********************************************************************/
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#ifndef __address_h
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@@ -330,20 +327,6 @@
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*/
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#define PHYS_PCI_V3_BASE 0x62000000
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-#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
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-
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-/* 'export' these to UHAL */
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-#define UHAL_PCI_IO PCI_IO_BASE
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-#define UHAL_PCI_MEM PCI_MEM_BASE
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-#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
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-#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
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-#define UHAL_PCI_MAX_SLOT 20
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-
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-/* ========================================================================
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- * Start of uHAL definitions
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- * ========================================================================
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- */
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-
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/* ------------------------------------------------------------------------
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* Integrator Interrupt Controllers
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* ------------------------------------------------------------------------
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@@ -391,7 +374,7 @@
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*/
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/* ------------------------------------------------------------------------
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- * LED's - The header LED is not accessible via the uHAL API
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+ * LED's
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* ------------------------------------------------------------------------
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*
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*/
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@@ -403,35 +386,19 @@
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#define LED_BANK INTEGRATOR_DBG_LEDS
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-/*
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- * Memory definitions - run uHAL out of SSRAM.
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- *
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- */
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-#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
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-
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-/*
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- * Clean base - dummy
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- *
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- */
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-#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
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-
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/*
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* Timer definitions
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*
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* Only use timer 1 & 2
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* (both run at 24MHz and will need the clock divider set to 16).
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*
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- * Timer 0 runs at bus frequency and therefore could vary and currently
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- * uHAL can't handle that.
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- *
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+ * Timer 0 runs at bus frequency
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*/
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#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
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#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
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#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
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-#define MAX_TIMER 2
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-#define MAX_PERIOD 699050
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#define TICKS_PER_uSEC 24
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/*
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@@ -439,14 +406,9 @@
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*
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*/
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#define mSEC_1 1000
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-#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
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-#define mSEC_25 (mSEC_1 * 25)
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-#define SEC_1 (mSEC_1 * 1000)
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#define INTEGRATOR_CSR_BASE 0x10000000
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#define INTEGRATOR_CSR_SIZE 0x10000000
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#endif
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-
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-/* END */
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