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@@ -849,20 +849,6 @@ static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
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return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
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}
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-#define first_dma_cap(mask) __first_dma_cap(&(mask))
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-static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
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-{
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- return min_t(int, DMA_TX_TYPE_END,
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- find_first_bit(srcp->bits, DMA_TX_TYPE_END));
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-}
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-
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-#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
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-static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
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-{
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- return min_t(int, DMA_TX_TYPE_END,
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- find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
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-}
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-
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#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
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static inline void
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__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
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@@ -891,9 +877,7 @@ __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
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}
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#define for_each_dma_cap_mask(cap, mask) \
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- for ((cap) = first_dma_cap(mask); \
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- (cap) < DMA_TX_TYPE_END; \
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- (cap) = next_dma_cap((cap), (mask)))
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+ for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
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/**
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* dma_async_issue_pending - flush pending transactions to HW
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