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@@ -25,6 +25,7 @@
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#define ATH9K_CLOCK_RATE_CCK 22
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#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
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#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
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+#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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@@ -90,7 +91,11 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
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return usecs *ATH9K_CLOCK_RATE_CCK;
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if (conf->channel->band == IEEE80211_BAND_2GHZ)
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return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
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- return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
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+
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+ if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
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+ return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
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+ else
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+ return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}
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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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@@ -2188,7 +2193,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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}
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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- pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
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+ pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
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+ ATH9K_HW_CAP_FASTCLOCK;
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pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
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pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
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pCap->rx_status_len = sizeof(struct ar9003_rxs);
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