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@@ -220,20 +220,7 @@ void __init omap_map_sram(void)
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if (omap_sram_size == 0)
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return;
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- if (cpu_is_omap24xx()) {
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- omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
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-
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- base = OMAP2_SRAM_PA;
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- base = ROUND_DOWN(base, PAGE_SIZE);
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- omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
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- }
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-
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if (cpu_is_omap34xx()) {
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- omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
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- base = OMAP3_SRAM_PA;
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- base = ROUND_DOWN(base, PAGE_SIZE);
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- omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
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-
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/*
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* SRAM must be marked as non-cached on OMAP3 since the
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* CORE DPLL M2 divider change code (in SRAM) runs with the
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@@ -244,13 +231,11 @@ void __init omap_map_sram(void)
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omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
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}
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- if (cpu_is_omap44xx()) {
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- omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
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- base = OMAP4_SRAM_PA;
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- base = ROUND_DOWN(base, PAGE_SIZE);
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- omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
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- }
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- omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
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+ omap_sram_io_desc[0].virtual = omap_sram_base;
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+ base = omap_sram_start;
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+ base = ROUND_DOWN(base, PAGE_SIZE);
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+ omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
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+ omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
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iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
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printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
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