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@@ -174,7 +174,7 @@ MODULE_DESCRIPTION("Intel HDA driver");
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#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
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#define ICH6_REG_INTCTL 0x20
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#define ICH6_REG_INTSTS 0x24
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-#define ICH6_REG_WALCLK 0x30
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+#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
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#define ICH6_REG_SYNC 0x34
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#define ICH6_REG_CORBLBASE 0x40
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#define ICH6_REG_CORBUBASE 0x44
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@@ -340,8 +340,8 @@ struct azx_dev {
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unsigned int period_bytes; /* size of the period in bytes */
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unsigned int frags; /* number for period in the play buffer */
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unsigned int fifo_size; /* FIFO size */
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- unsigned long start_jiffies; /* start + minimum jiffies */
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- unsigned long min_jiffies; /* minimum jiffies before position is valid */
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+ unsigned long start_wallclk; /* start + minimum wallclk */
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+ unsigned long period_wallclk; /* wallclk for period */
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void __iomem *sd_addr; /* stream descriptor pointer */
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@@ -361,7 +361,6 @@ struct azx_dev {
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unsigned int opened :1;
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unsigned int running :1;
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unsigned int irq_pending :1;
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- unsigned int start_flag: 1; /* stream full start flag */
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/*
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* For VIA:
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* A flag to ensure DMA position is 0
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@@ -1676,8 +1675,9 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
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return err;
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}
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- azx_dev->min_jiffies = (runtime->period_size * HZ) /
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- (runtime->rate * 2);
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+ /* wallclk has 24Mhz clock source */
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+ azx_dev->period_wallclk = (((runtime->period_size * 24000) /
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+ runtime->rate) * 1000);
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azx_setup_controller(chip, azx_dev);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
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@@ -1731,14 +1731,15 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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if (s->pcm->card != substream->pcm->card)
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continue;
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azx_dev = get_azx_dev(s);
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- if (rstart) {
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- azx_dev->start_flag = 1;
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- azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
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- }
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- if (start)
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+ if (start) {
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+ azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
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+ if (!rstart)
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+ azx_dev->start_wallclk -=
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+ azx_dev->period_wallclk;
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azx_stream_start(chip, azx_dev);
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- else
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+ } else {
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azx_stream_stop(chip, azx_dev);
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+ }
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azx_dev->running = start;
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}
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spin_unlock(&chip->reg_lock);
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@@ -1885,13 +1886,14 @@ static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
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*/
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static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
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{
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+ u32 wallclk;
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unsigned int pos;
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int stream;
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- if (azx_dev->start_flag &&
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- time_before_eq(jiffies, azx_dev->start_jiffies))
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+ wallclk = azx_readl(chip, WALLCLK);
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+ if ((wallclk - azx_dev->start_wallclk) <
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+ (azx_dev->period_wallclk * 2) / 3)
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return -1; /* bogus (too early) interrupt */
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- azx_dev->start_flag = 0;
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stream = azx_dev->substream->stream;
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pos = azx_get_position(chip, azx_dev);
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@@ -1906,13 +1908,12 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
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chip->position_fix[stream] = POS_FIX_POSBUF;
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}
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- if (!bdl_pos_adj[chip->dev_index])
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- return 1; /* no delayed ack */
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if (WARN_ONCE(!azx_dev->period_bytes,
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"hda-intel: zero azx_dev->period_bytes"))
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return 0; /* this shouldn't happen! */
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if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
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return 0; /* NG - it's below the period boundary */
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+ azx_dev->start_wallclk = wallclk;
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return 1; /* OK, it's fine */
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}
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@@ -1922,7 +1923,7 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
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static void azx_irq_pending_work(struct work_struct *work)
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{
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struct azx *chip = container_of(work, struct azx, irq_pending_work);
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- int i, pending;
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+ int i, pending, ok;
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if (!chip->irq_pending_warned) {
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printk(KERN_WARNING
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@@ -1941,11 +1942,14 @@ static void azx_irq_pending_work(struct work_struct *work)
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!azx_dev->substream ||
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!azx_dev->running)
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continue;
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- if (azx_position_ok(chip, azx_dev)) {
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+ ok = azx_position_ok(chip, azx_dev);
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+ if (ok > 0) {
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azx_dev->irq_pending = 0;
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spin_unlock(&chip->reg_lock);
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snd_pcm_period_elapsed(azx_dev->substream);
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spin_lock(&chip->reg_lock);
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+ } else if (ok < 0) {
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+ pending = 0; /* too early */
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} else
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pending++;
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}
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