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@@ -0,0 +1,461 @@
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+/*
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+ * intel_idle.c - native hardware idle loop for modern Intel processors
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+ *
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+ * Copyright (c) 2010, Intel Corporation.
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+ * Len Brown <len.brown@intel.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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+ */
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+
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+/*
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+ * intel_idle is a cpuidle driver that loads on specific Intel processors
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+ * in lieu of the legacy ACPI processor_idle driver. The intent is to
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+ * make Linux more efficient on these processors, as intel_idle knows
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+ * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
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+ */
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+
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+/*
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+ * Design Assumptions
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+ *
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+ * All CPUs have same idle states as boot CPU
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+ *
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+ * Chipset BM_STS (bus master status) bit is a NOP
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+ * for preventing entry into deep C-stats
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+ */
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+
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+/*
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+ * Known limitations
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+ *
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+ * The driver currently initializes for_each_online_cpu() upon modprobe.
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+ * It it unaware of subsequent processors hot-added to the system.
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+ * This means that if you boot with maxcpus=n and later online
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+ * processors above n, those processors will use C1 only.
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+ *
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+ * ACPI has a .suspend hack to turn off deep c-statees during suspend
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+ * to avoid complications with the lapic timer workaround.
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+ * Have not seen issues with suspend, but may need same workaround here.
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+ *
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+ * There is currently no kernel-based automatic probing/loading mechanism
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+ * if the driver is built as a module.
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+ */
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+
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+/* un-comment DEBUG to enable pr_debug() statements */
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+#define DEBUG
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+
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+#include <linux/kernel.h>
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+#include <linux/cpuidle.h>
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+#include <linux/clockchips.h>
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+#include <linux/hrtimer.h> /* ktime_get_real() */
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+#include <trace/events/power.h>
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+#include <linux/sched.h>
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+
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+#define INTEL_IDLE_VERSION "0.4"
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+#define PREFIX "intel_idle: "
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+
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+#define MWAIT_SUBSTATE_MASK (0xf)
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+#define MWAIT_CSTATE_MASK (0xf)
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+#define MWAIT_SUBSTATE_SIZE (4)
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+#define MWAIT_MAX_NUM_CSTATES 8
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+#define CPUID_MWAIT_LEAF (5)
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+#define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
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+#define CPUID5_ECX_INTERRUPT_BREAK (0x2)
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+
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+static struct cpuidle_driver intel_idle_driver = {
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+ .name = "intel_idle",
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+ .owner = THIS_MODULE,
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+};
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+/* intel_idle.max_cstate=0 disables driver */
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+static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
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+static int power_policy = 7; /* 0 = max perf; 15 = max powersave */
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+
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+static unsigned int substates;
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+static int (*choose_substate)(int);
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+
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+/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
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+static unsigned int lapic_timer_reliable_states;
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+
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+static struct cpuidle_device *intel_idle_cpuidle_devices;
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+static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
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+
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+static struct cpuidle_state *cpuidle_state_table;
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+
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+/*
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+ * States are indexed by the cstate number,
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+ * which is also the index into the MWAIT hint array.
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+ * Thus C0 is a dummy.
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+ */
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+static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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+ { /* MWAIT C0 */ },
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+ { /* MWAIT C1 */
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+ .name = "NHM-C1",
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+ .desc = "MWAIT 0x00",
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+ .driver_data = (void *) 0x00,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 3,
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+ .power_usage = 1000,
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+ .target_residency = 6,
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+ .enter = &intel_idle },
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+ { /* MWAIT C2 */
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+ .name = "NHM-C3",
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+ .desc = "MWAIT 0x10",
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+ .driver_data = (void *) 0x10,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 20,
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+ .power_usage = 500,
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+ .target_residency = 80,
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+ .enter = &intel_idle },
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+ { /* MWAIT C3 */
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+ .name = "NHM-C6",
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+ .desc = "MWAIT 0x20",
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+ .driver_data = (void *) 0x20,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 200,
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+ .power_usage = 350,
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+ .target_residency = 800,
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+ .enter = &intel_idle },
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+};
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+
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+static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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+ { /* MWAIT C0 */ },
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+ { /* MWAIT C1 */
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+ .name = "ATM-C1",
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+ .desc = "MWAIT 0x00",
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+ .driver_data = (void *) 0x00,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 1,
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+ .power_usage = 1000,
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+ .target_residency = 4,
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+ .enter = &intel_idle },
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+ { /* MWAIT C2 */
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+ .name = "ATM-C2",
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+ .desc = "MWAIT 0x10",
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+ .driver_data = (void *) 0x10,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 20,
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+ .power_usage = 500,
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+ .target_residency = 80,
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+ .enter = &intel_idle },
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+ { /* MWAIT C3 */ },
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+ { /* MWAIT C4 */
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+ .name = "ATM-C4",
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+ .desc = "MWAIT 0x30",
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+ .driver_data = (void *) 0x30,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 100,
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+ .power_usage = 250,
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+ .target_residency = 400,
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+ .enter = &intel_idle },
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+ { /* MWAIT C5 */ },
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+ { /* MWAIT C6 */
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+ .name = "ATM-C6",
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+ .desc = "MWAIT 0x40",
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+ .driver_data = (void *) 0x40,
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+ .flags = CPUIDLE_FLAG_TIME_VALID,
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+ .exit_latency = 200,
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+ .power_usage = 150,
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+ .target_residency = 800,
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+ .enter = NULL }, /* disabled */
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+};
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+
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+/*
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+ * choose_tunable_substate()
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+ *
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+ * Run-time decision on which C-state substate to invoke
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+ * If power_policy = 0, choose shallowest substate (0)
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+ * If power_policy = 15, choose deepest substate
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+ * If power_policy = middle, choose middle substate etc.
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+ */
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+static int choose_tunable_substate(int cstate)
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+{
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+ unsigned int num_substates;
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+ unsigned int substate_choice;
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+
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+ power_policy &= 0xF; /* valid range: 0-15 */
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+ cstate &= 7; /* valid range: 0-7 */
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+
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+ num_substates = (substates >> ((cstate) * 4)) & MWAIT_SUBSTATE_MASK;
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+
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+ if (num_substates <= 1)
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+ return 0;
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+
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+ substate_choice = ((power_policy + (power_policy + 1) *
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+ (num_substates - 1)) / 16);
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+
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+ return substate_choice;
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+}
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+
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+/*
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+ * choose_zero_substate()
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+ */
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+static int choose_zero_substate(int cstate)
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+{
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+ return 0;
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+}
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+
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+/**
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+ * intel_idle
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+ * @dev: cpuidle_device
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+ * @state: cpuidle state
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+ *
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+ */
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+static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
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+{
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+ unsigned long ecx = 1; /* break on interrupt flag */
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+ unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
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+ unsigned int cstate;
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+ ktime_t kt_before, kt_after;
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+ s64 usec_delta;
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+ int cpu = smp_processor_id();
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+
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+ cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
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+
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+ eax = eax + (choose_substate)(cstate);
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+
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+ local_irq_disable();
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+
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+ if (!(lapic_timer_reliable_states & (1 << (cstate))))
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+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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+
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+ kt_before = ktime_get_real();
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+
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+ stop_critical_timings();
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+#ifndef MODULE
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+ trace_power_start(POWER_CSTATE, (eax >> 4) + 1);
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+#endif
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+ if (!need_resched()) {
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+
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+ __monitor((void *)¤t_thread_info()->flags, 0, 0);
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+ smp_mb();
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+ if (!need_resched())
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+ __mwait(eax, ecx);
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+ }
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+
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+ start_critical_timings();
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+
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+ kt_after = ktime_get_real();
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+ usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
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+
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+ local_irq_enable();
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+
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+ if (!(lapic_timer_reliable_states & (1 << (cstate))))
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+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
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+
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+ return usec_delta;
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+}
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+
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+/*
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+ * intel_idle_probe()
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+ */
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+static int intel_idle_probe(void)
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+{
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+ unsigned int eax, ebx, ecx, edx;
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+
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+ if (max_cstate == 0) {
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+ pr_debug(PREFIX "disabled\n");
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+ return -EPERM;
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+ }
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+
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+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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+ return -ENODEV;
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+
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+ if (!boot_cpu_has(X86_FEATURE_MWAIT))
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+ return -ENODEV;
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+
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+ if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
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+ return -ENODEV;
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+
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+ cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
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+
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+ if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
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+ !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
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+ return -ENODEV;
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+#ifdef DEBUG
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+ if (substates == 0) /* can over-ride via modparam */
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+#endif
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+ substates = edx;
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+
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+ pr_debug(PREFIX "MWAIT substates: 0x%x\n", substates);
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+
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+ if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
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+ lapic_timer_reliable_states = 0xFFFFFFFF;
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+
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+ if (boot_cpu_data.x86 != 6) /* family 6 */
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+ return -ENODEV;
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+
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+ switch (boot_cpu_data.x86_model) {
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+
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+ case 0x1A: /* Core i7, Xeon 5500 series */
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+ case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
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+ case 0x1F: /* Core i7 and i5 Processor - Nehalem */
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+ case 0x2E: /* Nehalem-EX Xeon */
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+ lapic_timer_reliable_states = (1 << 1); /* C1 */
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+
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+ case 0x25: /* Westmere */
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+ case 0x2C: /* Westmere */
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+ cpuidle_state_table = nehalem_cstates;
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+ choose_substate = choose_tunable_substate;
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+ break;
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+
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+ case 0x1C: /* 28 - Atom Processor */
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+ lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
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+ cpuidle_state_table = atom_cstates;
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+ choose_substate = choose_zero_substate;
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+ break;
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+#ifdef FUTURE_USE
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+ case 0x17: /* 23 - Core 2 Duo */
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+ lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
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+#endif
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+
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+ default:
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+ pr_debug(PREFIX "does not run on family %d model %d\n",
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+ boot_cpu_data.x86, boot_cpu_data.x86_model);
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+ return -ENODEV;
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+ }
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+
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+ pr_debug(PREFIX "v" INTEL_IDLE_VERSION
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+ " model 0x%X\n", boot_cpu_data.x86_model);
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+
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+ pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
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+ lapic_timer_reliable_states);
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+ return 0;
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+}
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+
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+/*
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+ * intel_idle_cpuidle_devices_uninit()
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+ * unregister, free cpuidle_devices
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+ */
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+static void intel_idle_cpuidle_devices_uninit(void)
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+{
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+ int i;
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+ struct cpuidle_device *dev;
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+
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+ for_each_online_cpu(i) {
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+ dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
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+ cpuidle_unregister_device(dev);
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+ }
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+
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+ free_percpu(intel_idle_cpuidle_devices);
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+ return;
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+}
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+/*
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+ * intel_idle_cpuidle_devices_init()
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+ * allocate, initialize, register cpuidle_devices
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+ */
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+static int intel_idle_cpuidle_devices_init(void)
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+{
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+ int i, cstate;
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+ struct cpuidle_device *dev;
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+
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+ intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
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+ if (intel_idle_cpuidle_devices == NULL)
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+ return -ENOMEM;
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+
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+ for_each_online_cpu(i) {
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+ dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
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+
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+ dev->state_count = 1;
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+
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+ for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
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+ int num_substates;
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+
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+ if (cstate > max_cstate) {
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+ printk(PREFIX "max_cstate %d reached\n",
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+ max_cstate);
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+ break;
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+ }
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+
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+ /* does the state exist in CPUID.MWAIT? */
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+ num_substates = (substates >> ((cstate) * 4))
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+ & MWAIT_SUBSTATE_MASK;
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+ if (num_substates == 0)
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+ continue;
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+ /* is the state not enabled? */
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+ if (cpuidle_state_table[cstate].enter == NULL) {
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+ /* does the driver not know about the state? */
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+ if (*cpuidle_state_table[cstate].name == '\0')
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+ pr_debug(PREFIX "unaware of model 0x%x"
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+ " MWAIT %d please"
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+ " contact lenb@kernel.org",
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+ boot_cpu_data.x86_model, cstate);
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+ continue;
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+ }
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+
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+ if ((cstate > 2) &&
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+ !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
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+ mark_tsc_unstable("TSC halts in idle"
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+ " states deeper than C2");
|
|
|
+
|
|
|
+ dev->states[dev->state_count] = /* structure copy */
|
|
|
+ cpuidle_state_table[cstate];
|
|
|
+
|
|
|
+ dev->state_count += 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev->cpu = i;
|
|
|
+ if (cpuidle_register_device(dev)) {
|
|
|
+ pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
|
|
|
+ i);
|
|
|
+ intel_idle_cpuidle_devices_uninit();
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static int __init intel_idle_init(void)
|
|
|
+{
|
|
|
+ int retval;
|
|
|
+
|
|
|
+ retval = intel_idle_probe();
|
|
|
+ if (retval)
|
|
|
+ return retval;
|
|
|
+
|
|
|
+ retval = cpuidle_register_driver(&intel_idle_driver);
|
|
|
+ if (retval) {
|
|
|
+ printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
|
|
|
+ cpuidle_get_driver()->name);
|
|
|
+ return retval;
|
|
|
+ }
|
|
|
+
|
|
|
+ retval = intel_idle_cpuidle_devices_init();
|
|
|
+ if (retval) {
|
|
|
+ cpuidle_unregister_driver(&intel_idle_driver);
|
|
|
+ return retval;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void __exit intel_idle_exit(void)
|
|
|
+{
|
|
|
+ intel_idle_cpuidle_devices_uninit();
|
|
|
+ cpuidle_unregister_driver(&intel_idle_driver);
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+module_init(intel_idle_init);
|
|
|
+module_exit(intel_idle_exit);
|
|
|
+
|
|
|
+module_param(power_policy, int, 0644);
|
|
|
+module_param(max_cstate, int, 0444);
|
|
|
+#ifdef DEBUG
|
|
|
+module_param(substates, int, 0444);
|
|
|
+#endif
|
|
|
+
|
|
|
+MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
|
|
|
+MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
|
|
|
+MODULE_LICENSE("GPL");
|
Linus Torvalds