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@@ -55,318 +55,318 @@
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/* Ethernet Unit Registers */
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/****************************************/
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-#define MV643XX_ETH_PHY_ADDR_REG 0x0000
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-#define MV643XX_ETH_SMI_REG 0x0004
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-#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x0008
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-#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x000c
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-#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x0080
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-#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x0084
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-#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x04fc
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-#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x0094
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-#define MV643XX_ETH_BAR_0 0x0200
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-#define MV643XX_ETH_BAR_1 0x0208
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-#define MV643XX_ETH_BAR_2 0x0210
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-#define MV643XX_ETH_BAR_3 0x0218
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-#define MV643XX_ETH_BAR_4 0x0220
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-#define MV643XX_ETH_BAR_5 0x0228
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-#define MV643XX_ETH_SIZE_REG_0 0x0204
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-#define MV643XX_ETH_SIZE_REG_1 0x020c
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-#define MV643XX_ETH_SIZE_REG_2 0x0214
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-#define MV643XX_ETH_SIZE_REG_3 0x021c
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-#define MV643XX_ETH_SIZE_REG_4 0x0224
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-#define MV643XX_ETH_SIZE_REG_5 0x022c
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-#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x0230
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-#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x0234
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-#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x0280
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-#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x0284
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-#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x0288
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-#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x028c
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-#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x0290
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-#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x0294 + (port<<2))
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-#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x1000 + (port<<7))
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-#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x0400 + (port<<10))
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-#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x0404 + (port<<10))
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-#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x0408 + (port<<10))
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-#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x040c + (port<<10))
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-#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x0410 + (port<<10))
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-#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x0414 + (port<<10))
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-#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x0418 + (port<<10))
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-#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x041c + (port<<10))
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-#define MV643XX_ETH_DSCP_0(port) (0x0420 + (port<<10))
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-#define MV643XX_ETH_DSCP_1(port) (0x0424 + (port<<10))
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-#define MV643XX_ETH_DSCP_2(port) (0x0428 + (port<<10))
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-#define MV643XX_ETH_DSCP_3(port) (0x042c + (port<<10))
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-#define MV643XX_ETH_DSCP_4(port) (0x0430 + (port<<10))
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-#define MV643XX_ETH_DSCP_5(port) (0x0434 + (port<<10))
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-#define MV643XX_ETH_DSCP_6(port) (0x0438 + (port<<10))
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-#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x043c + (port<<10))
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-#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x0440 + (port<<10))
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-#define MV643XX_ETH_PORT_STATUS_REG(port) (0x0444 + (port<<10))
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-#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x0448 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x044c + (port<<10))
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-#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x0450 + (port<<10))
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-#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x0458 + (port<<10))
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-#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x045c + (port<<10))
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-#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x0460 + (port<<10))
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-#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x0464 + (port<<10))
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-#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x0468 + (port<<10))
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-#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x046c + (port<<10))
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-#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x0470 + (port<<10))
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-#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x0474 + (port<<10))
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-#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x047c + (port<<10))
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-#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x0484 + (port<<10))
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-#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x048c + (port<<10))
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-#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x0490 + (port<<10))
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-#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x0494 + (port<<10))
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-#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x04fc + (port<<10))
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-#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x0680 + (port<<10))
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-#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x0684 + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x060c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x061c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x062c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x063c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x064c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x065c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x066c + (port<<10))
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-#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x067c + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x06c0 + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x06c4 + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x06c8 + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x06cc + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x06d0 + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x06d4 + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x06d8 + (port<<10))
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-#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x06dc + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x0700 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x0710 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x0720 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x0730 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x0740 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x0750 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x0760 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x0770 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x0704 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x0714 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x0724 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x0734 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x0744 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x0754 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x0764 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x0774 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x0708 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x0718 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x0728 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x0738 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x0748 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x0758 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x0768 + (port<<10))
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-#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x0778 + (port<<10))
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-#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x0780 + (port<<10))
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-#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x1400 + (port<<10))
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-#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x1500 + (port<<10))
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-#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x1600 + (port<<10))
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+#define PHY_ADDR_REG 0x0000
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+#define SMI_REG 0x0004
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+#define UNIT_DEFAULT_ADDR_REG 0x0008
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+#define UNIT_DEFAULTID_REG 0x000c
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+#define UNIT_INTERRUPT_CAUSE_REG 0x0080
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+#define UNIT_INTERRUPT_MASK_REG 0x0084
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+#define UNIT_INTERNAL_USE_REG 0x04fc
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+#define UNIT_ERROR_ADDR_REG 0x0094
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+#define BAR_0 0x0200
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+#define BAR_1 0x0208
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+#define BAR_2 0x0210
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+#define BAR_3 0x0218
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+#define BAR_4 0x0220
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+#define BAR_5 0x0228
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+#define SIZE_REG_0 0x0204
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+#define SIZE_REG_1 0x020c
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+#define SIZE_REG_2 0x0214
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+#define SIZE_REG_3 0x021c
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+#define SIZE_REG_4 0x0224
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+#define SIZE_REG_5 0x022c
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+#define HEADERS_RETARGET_BASE_REG 0x0230
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+#define HEADERS_RETARGET_CONTROL_REG 0x0234
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+#define HIGH_ADDR_REMAP_REG_0 0x0280
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+#define HIGH_ADDR_REMAP_REG_1 0x0284
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+#define HIGH_ADDR_REMAP_REG_2 0x0288
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+#define HIGH_ADDR_REMAP_REG_3 0x028c
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+#define BASE_ADDR_ENABLE_REG 0x0290
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+#define ACCESS_PROTECTION_REG(port) (0x0294 + (port<<2))
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+#define MIB_COUNTERS_BASE(port) (0x1000 + (port<<7))
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+#define PORT_CONFIG_REG(port) (0x0400 + (port<<10))
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+#define PORT_CONFIG_EXTEND_REG(port) (0x0404 + (port<<10))
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+#define MII_SERIAL_PARAMETRS_REG(port) (0x0408 + (port<<10))
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+#define GMII_SERIAL_PARAMETRS_REG(port) (0x040c + (port<<10))
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+#define VLAN_ETHERTYPE_REG(port) (0x0410 + (port<<10))
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+#define MAC_ADDR_LOW(port) (0x0414 + (port<<10))
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+#define MAC_ADDR_HIGH(port) (0x0418 + (port<<10))
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+#define SDMA_CONFIG_REG(port) (0x041c + (port<<10))
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+#define DSCP_0(port) (0x0420 + (port<<10))
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+#define DSCP_1(port) (0x0424 + (port<<10))
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+#define DSCP_2(port) (0x0428 + (port<<10))
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+#define DSCP_3(port) (0x042c + (port<<10))
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+#define DSCP_4(port) (0x0430 + (port<<10))
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+#define DSCP_5(port) (0x0434 + (port<<10))
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+#define DSCP_6(port) (0x0438 + (port<<10))
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+#define PORT_SERIAL_CONTROL_REG(port) (0x043c + (port<<10))
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+#define VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x0440 + (port<<10))
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+#define PORT_STATUS_REG(port) (0x0444 + (port<<10))
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+#define TRANSMIT_QUEUE_COMMAND_REG(port) (0x0448 + (port<<10))
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+#define TX_QUEUE_FIXED_PRIORITY(port) (0x044c + (port<<10))
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+#define PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x0450 + (port<<10))
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+#define MAXIMUM_TRANSMIT_UNIT(port) (0x0458 + (port<<10))
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+#define PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x045c + (port<<10))
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+#define INTERRUPT_CAUSE_REG(port) (0x0460 + (port<<10))
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+#define INTERRUPT_CAUSE_EXTEND_REG(port) (0x0464 + (port<<10))
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+#define INTERRUPT_MASK_REG(port) (0x0468 + (port<<10))
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+#define INTERRUPT_EXTEND_MASK_REG(port) (0x046c + (port<<10))
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+#define RX_FIFO_URGENT_THRESHOLD_REG(port) (0x0470 + (port<<10))
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+#define TX_FIFO_URGENT_THRESHOLD_REG(port) (0x0474 + (port<<10))
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+#define RX_MINIMAL_FRAME_SIZE_REG(port) (0x047c + (port<<10))
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+#define RX_DISCARDED_FRAMES_COUNTER(port) (0x0484 + (port<<10))
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+#define PORT_DEBUG_0_REG(port) (0x048c + (port<<10))
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+#define PORT_DEBUG_1_REG(port) (0x0490 + (port<<10))
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+#define PORT_INTERNAL_ADDR_ERROR_REG(port) (0x0494 + (port<<10))
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+#define INTERNAL_USE_REG(port) (0x04fc + (port<<10))
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+#define RECEIVE_QUEUE_COMMAND_REG(port) (0x0680 + (port<<10))
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+#define CURRENT_SERVED_TX_DESC_PTR(port) (0x0684 + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x060c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x061c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x062c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x063c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x064c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x065c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x066c + (port<<10))
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+#define RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x067c + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x06c0 + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x06c4 + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x06c8 + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x06cc + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x06d0 + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x06d4 + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x06d8 + (port<<10))
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+#define TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x06dc + (port<<10))
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+#define TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x0700 + (port<<10))
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+#define TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x0710 + (port<<10))
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+#define TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x0720 + (port<<10))
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+#define TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x0730 + (port<<10))
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+#define TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x0740 + (port<<10))
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+#define TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x0750 + (port<<10))
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+#define TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x0760 + (port<<10))
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+#define TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x0770 + (port<<10))
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+#define TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x0704 + (port<<10))
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+#define TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x0714 + (port<<10))
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+#define TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x0724 + (port<<10))
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+#define TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x0734 + (port<<10))
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+#define TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x0744 + (port<<10))
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+#define TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x0754 + (port<<10))
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+#define TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x0764 + (port<<10))
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+#define TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x0774 + (port<<10))
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+#define TX_QUEUE_0_ARBITER_CONFIG(port) (0x0708 + (port<<10))
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+#define TX_QUEUE_1_ARBITER_CONFIG(port) (0x0718 + (port<<10))
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+#define TX_QUEUE_2_ARBITER_CONFIG(port) (0x0728 + (port<<10))
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+#define TX_QUEUE_3_ARBITER_CONFIG(port) (0x0738 + (port<<10))
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|
|
+#define TX_QUEUE_4_ARBITER_CONFIG(port) (0x0748 + (port<<10))
|
|
|
+#define TX_QUEUE_5_ARBITER_CONFIG(port) (0x0758 + (port<<10))
|
|
|
+#define TX_QUEUE_6_ARBITER_CONFIG(port) (0x0768 + (port<<10))
|
|
|
+#define TX_QUEUE_7_ARBITER_CONFIG(port) (0x0778 + (port<<10))
|
|
|
+#define PORT_TX_TOKEN_BUCKET_COUNT(port) (0x0780 + (port<<10))
|
|
|
+#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x1400 + (port<<10))
|
|
|
+#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x1500 + (port<<10))
|
|
|
+#define DA_FILTER_UNICAST_TABLE_BASE(port) (0x1600 + (port<<10))
|
|
|
|
|
|
/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
|
|
|
-#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
|
|
|
-#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
|
|
|
-#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
|
|
|
-#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
|
|
|
-#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
|
|
|
-#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
|
|
|
-#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
|
|
|
-#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
|
|
|
-#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
|
|
|
-#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
|
|
|
-#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
|
|
|
-#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
|
|
|
-#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
|
|
|
-#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
|
|
|
-
|
|
|
-#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
|
|
|
- MV643XX_ETH_UNICAST_NORMAL_MODE | \
|
|
|
- MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
|
|
|
- MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
|
|
|
- MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
|
|
|
- MV643XX_ETH_RECEIVE_BC_IF_IP | \
|
|
|
- MV643XX_ETH_RECEIVE_BC_IF_ARP | \
|
|
|
- MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
|
|
|
- MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
|
|
|
- MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
|
|
|
- MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
|
|
|
- MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
|
|
|
+#define UNICAST_NORMAL_MODE 0
|
|
|
+#define UNICAST_PROMISCUOUS_MODE (1<<0)
|
|
|
+#define DEFAULT_RX_QUEUE_0 0
|
|
|
+#define DEFAULT_RX_QUEUE_1 (1<<1)
|
|
|
+#define DEFAULT_RX_QUEUE_2 (1<<2)
|
|
|
+#define DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
|
|
|
+#define DEFAULT_RX_QUEUE_4 (1<<3)
|
|
|
+#define DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
|
|
|
+#define DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
|
|
|
+#define DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_0 0
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_1 (1<<4)
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_2 (1<<5)
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_4 (1<<6)
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
|
|
|
+#define DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
|
|
|
+#define RECEIVE_BC_IF_NOT_IP_OR_ARP 0
|
|
|
+#define REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
|
|
|
+#define RECEIVE_BC_IF_IP 0
|
|
|
+#define REJECT_BC_IF_IP (1<<8)
|
|
|
+#define RECEIVE_BC_IF_ARP 0
|
|
|
+#define REJECT_BC_IF_ARP (1<<9)
|
|
|
+#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
|
|
|
+#define CAPTURE_TCP_FRAMES_DIS 0
|
|
|
+#define CAPTURE_TCP_FRAMES_EN (1<<14)
|
|
|
+#define CAPTURE_UDP_FRAMES_DIS 0
|
|
|
+#define CAPTURE_UDP_FRAMES_EN (1<<15)
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_0 0
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_1 (1<<16)
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_2 (1<<17)
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_4 (1<<18)
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
|
|
|
+#define DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_0 0
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_1 (1<<19)
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_2 (1<<20)
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_4 (1<<21)
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
|
|
|
+#define DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_0 0
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
|
|
|
+#define DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
|
|
|
+
|
|
|
+#define PORT_CONFIG_DEFAULT_VALUE \
|
|
|
+ UNICAST_NORMAL_MODE | \
|
|
|
+ DEFAULT_RX_QUEUE_0 | \
|
|
|
+ DEFAULT_RX_ARP_QUEUE_0 | \
|
|
|
+ RECEIVE_BC_IF_NOT_IP_OR_ARP | \
|
|
|
+ RECEIVE_BC_IF_IP | \
|
|
|
+ RECEIVE_BC_IF_ARP | \
|
|
|
+ CAPTURE_TCP_FRAMES_DIS | \
|
|
|
+ CAPTURE_UDP_FRAMES_DIS | \
|
|
|
+ DEFAULT_RX_TCP_QUEUE_0 | \
|
|
|
+ DEFAULT_RX_UDP_QUEUE_0 | \
|
|
|
+ DEFAULT_RX_BPDU_QUEUE_0
|
|
|
|
|
|
/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
|
|
|
-#define MV643XX_ETH_CLASSIFY_EN (1<<0)
|
|
|
-#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
|
|
|
-#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
|
|
|
-#define MV643XX_ETH_PARTITION_DISABLE 0
|
|
|
-#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
|
|
|
+#define CLASSIFY_EN (1<<0)
|
|
|
+#define SPAN_BPDU_PACKETS_AS_NORMAL 0
|
|
|
+#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
|
|
|
+#define PARTITION_DISABLE 0
|
|
|
+#define PARTITION_ENABLE (1<<2)
|
|
|
|
|
|
-#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
|
|
|
- MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
|
|
|
- MV643XX_ETH_PARTITION_DISABLE
|
|
|
+#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
|
|
|
+ SPAN_BPDU_PACKETS_AS_NORMAL | \
|
|
|
+ PARTITION_DISABLE
|
|
|
|
|
|
/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
|
|
|
-#define MV643XX_ETH_RIFB (1<<0)
|
|
|
-#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
|
|
|
-#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
|
|
|
-#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
|
|
|
-#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
|
|
|
-#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
|
|
|
-#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
|
|
|
-#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
|
|
|
-#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
|
|
|
-#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
|
|
|
-#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
|
|
|
-#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
|
|
|
-#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
|
|
|
-#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
|
|
|
-#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
|
|
|
-#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
|
|
|
-#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
|
|
|
-
|
|
|
-#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
|
|
|
+#define RIFB (1<<0)
|
|
|
+#define RX_BURST_SIZE_1_64BIT 0
|
|
|
+#define RX_BURST_SIZE_2_64BIT (1<<1)
|
|
|
+#define RX_BURST_SIZE_4_64BIT (1<<2)
|
|
|
+#define RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
|
|
|
+#define RX_BURST_SIZE_16_64BIT (1<<3)
|
|
|
+#define BLM_RX_NO_SWAP (1<<4)
|
|
|
+#define BLM_RX_BYTE_SWAP 0
|
|
|
+#define BLM_TX_NO_SWAP (1<<5)
|
|
|
+#define BLM_TX_BYTE_SWAP 0
|
|
|
+#define DESCRIPTORS_BYTE_SWAP (1<<6)
|
|
|
+#define DESCRIPTORS_NO_SWAP 0
|
|
|
+#define TX_BURST_SIZE_1_64BIT 0
|
|
|
+#define TX_BURST_SIZE_2_64BIT (1<<22)
|
|
|
+#define TX_BURST_SIZE_4_64BIT (1<<23)
|
|
|
+#define TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
|
|
|
+#define TX_BURST_SIZE_16_64BIT (1<<24)
|
|
|
+
|
|
|
+#define IPG_INT_RX(value) ((value & 0x3fff) << 8)
|
|
|
|
|
|
#if defined(__BIG_ENDIAN)
|
|
|
-#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
|
|
|
- MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
|
|
|
- MV643XX_ETH_IPG_INT_RX(0) | \
|
|
|
- MV643XX_ETH_TX_BURST_SIZE_4_64BIT
|
|
|
+#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
|
|
|
+ RX_BURST_SIZE_4_64BIT | \
|
|
|
+ IPG_INT_RX(0) | \
|
|
|
+ TX_BURST_SIZE_4_64BIT
|
|
|
#elif defined(__LITTLE_ENDIAN)
|
|
|
-#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
|
|
|
- MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
|
|
|
- MV643XX_ETH_BLM_RX_NO_SWAP | \
|
|
|
- MV643XX_ETH_BLM_TX_NO_SWAP | \
|
|
|
- MV643XX_ETH_IPG_INT_RX(0) | \
|
|
|
- MV643XX_ETH_TX_BURST_SIZE_4_64BIT
|
|
|
+#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
|
|
|
+ RX_BURST_SIZE_4_64BIT | \
|
|
|
+ BLM_RX_NO_SWAP | \
|
|
|
+ BLM_TX_NO_SWAP | \
|
|
|
+ IPG_INT_RX(0) | \
|
|
|
+ TX_BURST_SIZE_4_64BIT
|
|
|
#else
|
|
|
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
|
|
|
#endif
|
|
|
|
|
|
/* These macros describe Ethernet Port serial control reg (PSCR) bits */
|
|
|
-#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
|
|
|
-#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
|
|
|
-#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
|
|
|
-#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
|
|
|
-#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
|
|
|
-#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
|
|
|
-#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
|
|
|
-#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
|
|
|
-#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
|
|
|
-#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
|
|
|
-#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
|
|
|
-#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
|
|
|
-#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
|
|
|
-#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
|
|
|
-#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
|
|
|
-#define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
|
|
|
-#define MV643XX_ETH_FORCE_LINK_FAIL 0
|
|
|
-#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
|
|
|
-#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
|
|
|
-#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
|
|
|
-#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
|
|
|
-#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
|
|
|
-#define MV643XX_ETH_DTE_ADV_0 0
|
|
|
-#define MV643XX_ETH_DTE_ADV_1 (1<<14)
|
|
|
-#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
|
|
|
-#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
|
|
|
-#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
|
|
|
-#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
|
|
|
-#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
|
|
|
-#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
|
|
|
-#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
|
|
|
-#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
|
|
|
-#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
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-#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
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-#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
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-#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
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-#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
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-#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
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-#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
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-#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
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-#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
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-#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
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-#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
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-#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
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-
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-#define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
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-
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-#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
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- MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
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- MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
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- MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
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- MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
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- MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
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- MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
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+#define SERIAL_PORT_DISABLE 0
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+#define SERIAL_PORT_ENABLE (1<<0)
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+#define FORCE_LINK_PASS (1<<1)
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+#define DO_NOT_FORCE_LINK_PASS 0
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+#define ENABLE_AUTO_NEG_FOR_DUPLX 0
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+#define DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
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+#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
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+#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
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+#define ADV_NO_FLOW_CTRL 0
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+#define ADV_SYMMETRIC_FLOW_CTRL (1<<4)
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+#define FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
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+#define FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
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+#define FORCE_BP_MODE_NO_JAM 0
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+#define FORCE_BP_MODE_JAM_TX (1<<7)
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+#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
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+#define SERIAL_PORT_CONTROL_RESERVED (1<<9)
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+#define FORCE_LINK_FAIL 0
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+#define DO_NOT_FORCE_LINK_FAIL (1<<10)
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+#define RETRANSMIT_16_ATTEMPTS 0
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+#define RETRANSMIT_FOREVER (1<<11)
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+#define DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
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+#define ENABLE_AUTO_NEG_SPEED_GMII 0
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+#define DTE_ADV_0 0
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+#define DTE_ADV_1 (1<<14)
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+#define DISABLE_AUTO_NEG_BYPASS 0
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+#define ENABLE_AUTO_NEG_BYPASS (1<<15)
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+#define AUTO_NEG_NO_CHANGE 0
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+#define RESTART_AUTO_NEG (1<<16)
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+#define MAX_RX_PACKET_1518BYTE 0
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+#define MAX_RX_PACKET_1522BYTE (1<<17)
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+#define MAX_RX_PACKET_1552BYTE (1<<18)
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+#define MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
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+#define MAX_RX_PACKET_9192BYTE (1<<19)
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+#define MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
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+#define SET_EXT_LOOPBACK (1<<20)
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+#define CLR_EXT_LOOPBACK 0
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+#define SET_FULL_DUPLEX_MODE (1<<21)
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+#define SET_HALF_DUPLEX_MODE 0
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+#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
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+#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
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+#define SET_GMII_SPEED_TO_10_100 0
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+#define SET_GMII_SPEED_TO_1000 (1<<23)
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+#define SET_MII_SPEED_TO_10 0
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+#define SET_MII_SPEED_TO_100 (1<<24)
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+
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+#define MAX_RX_PACKET_MASK (0x7<<17)
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+
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+#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
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+ DO_NOT_FORCE_LINK_PASS | \
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+ ENABLE_AUTO_NEG_FOR_DUPLX | \
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+ DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
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+ ADV_SYMMETRIC_FLOW_CTRL | \
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+ FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
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+ FORCE_BP_MODE_NO_JAM | \
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(1<<9) /* reserved */ | \
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- MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
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- MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
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- MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
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- MV643XX_ETH_DTE_ADV_0 | \
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- MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
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- MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
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- MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
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- MV643XX_ETH_CLR_EXT_LOOPBACK | \
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- MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
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- MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
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+ DO_NOT_FORCE_LINK_FAIL | \
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+ RETRANSMIT_16_ATTEMPTS | \
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+ ENABLE_AUTO_NEG_SPEED_GMII | \
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+ DTE_ADV_0 | \
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+ DISABLE_AUTO_NEG_BYPASS | \
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+ AUTO_NEG_NO_CHANGE | \
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+ MAX_RX_PACKET_9700BYTE | \
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+ CLR_EXT_LOOPBACK | \
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+ SET_FULL_DUPLEX_MODE | \
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+ ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
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/* These macros describe Ethernet Serial Status reg (PSR) bits */
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-#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
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-#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
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-#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
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-#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
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-#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
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-#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
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+#define PORT_STATUS_MODE_10_BIT (1<<0)
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+#define PORT_STATUS_LINK_UP (1<<1)
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+#define PORT_STATUS_FULL_DUPLEX (1<<2)
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+#define PORT_STATUS_FLOW_CONTROL (1<<3)
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+#define PORT_STATUS_GMII_1000 (1<<4)
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+#define PORT_STATUS_MII_100 (1<<5)
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/* PSR bit 6 is undocumented */
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-#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
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-#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
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-#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
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-#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
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+#define PORT_STATUS_TX_IN_PROGRESS (1<<7)
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+#define PORT_STATUS_AUTONEG_BYPASSED (1<<8)
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+#define PORT_STATUS_PARTITION (1<<9)
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+#define PORT_STATUS_TX_FIFO_EMPTY (1<<10)
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/* PSR bits 11-31 are reserved */
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-#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
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-#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
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+#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
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+#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
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-#define MV643XX_ETH_DESC_SIZE 64
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+#define DESC_SIZE 64
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#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
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#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
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Lennert Buytenhek