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@@ -105,6 +105,10 @@
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#define E1000_FEXTNVM_SW_CONFIG 1
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#define E1000_FEXTNVM_SW_CONFIG 1
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#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
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#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
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+#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
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+#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
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+#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
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+
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#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
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#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
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#define E1000_ICH_RAR_ENTRIES 7
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#define E1000_ICH_RAR_ENTRIES 7
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@@ -125,6 +129,7 @@
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/* SMBus Address Phy Register */
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/* SMBus Address Phy Register */
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#define HV_SMB_ADDR PHY_REG(768, 26)
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#define HV_SMB_ADDR PHY_REG(768, 26)
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+#define HV_SMB_ADDR_MASK 0x007F
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#define HV_SMB_ADDR_PEC_EN 0x0200
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#define HV_SMB_ADDR_PEC_EN 0x0200
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#define HV_SMB_ADDR_VALID 0x0080
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#define HV_SMB_ADDR_VALID 0x0080
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@@ -237,6 +242,8 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
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static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
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static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
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+static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
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+static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
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static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
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static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
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{
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{
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@@ -272,7 +279,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
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static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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{
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{
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struct e1000_phy_info *phy = &hw->phy;
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struct e1000_phy_info *phy = &hw->phy;
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- u32 ctrl;
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+ u32 ctrl, fwsm;
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s32 ret_val = 0;
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s32 ret_val = 0;
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phy->addr = 1;
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phy->addr = 1;
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@@ -294,7 +301,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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* disabled, then toggle the LANPHYPC Value bit to force
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* disabled, then toggle the LANPHYPC Value bit to force
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* the interconnect to PCIe mode.
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* the interconnect to PCIe mode.
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*/
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*/
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- if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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+ fwsm = er32(FWSM);
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+ if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
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ctrl = er32(CTRL);
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ctrl = er32(CTRL);
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ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
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ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
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ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
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ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
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@@ -303,6 +311,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
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ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
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ew32(CTRL, ctrl);
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ew32(CTRL, ctrl);
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msleep(50);
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msleep(50);
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+
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+ /*
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+ * Gate automatic PHY configuration by hardware on
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+ * non-managed 82579
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+ */
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+ if (hw->mac.type == e1000_pch2lan)
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+ e1000_gate_hw_phy_config_ich8lan(hw, true);
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}
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}
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/*
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/*
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@@ -315,6 +330,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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if (ret_val)
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if (ret_val)
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goto out;
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goto out;
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+ /* Ungate automatic PHY configuration on non-managed 82579 */
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+ if ((hw->mac.type == e1000_pch2lan) &&
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+ !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
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+ msleep(10);
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+ e1000_gate_hw_phy_config_ich8lan(hw, false);
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+ }
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+
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phy->id = e1000_phy_unknown;
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phy->id = e1000_phy_unknown;
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ret_val = e1000e_get_phy_id(hw);
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ret_val = e1000e_get_phy_id(hw);
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if (ret_val)
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if (ret_val)
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@@ -561,13 +583,10 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
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if (mac->type == e1000_ich8lan)
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if (mac->type == e1000_ich8lan)
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e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
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e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
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- /* Disable PHY configuration by hardware, config by software */
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- if (mac->type == e1000_pch2lan) {
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- u32 extcnf_ctrl = er32(EXTCNF_CTRL);
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-
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- extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
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- ew32(EXTCNF_CTRL, extcnf_ctrl);
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- }
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+ /* Gate automatic PHY configuration by hardware on managed 82579 */
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+ if ((mac->type == e1000_pch2lan) &&
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+ (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
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+ e1000_gate_hw_phy_config_ich8lan(hw, true);
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return 0;
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return 0;
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}
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}
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@@ -652,6 +671,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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goto out;
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goto out;
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}
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}
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+ if (hw->mac.type == e1000_pch2lan) {
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+ ret_val = e1000_k1_workaround_lv(hw);
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+ if (ret_val)
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+ goto out;
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+ }
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+
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/*
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/*
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* Check if there was DownShift, must be checked
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* Check if there was DownShift, must be checked
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* immediately after link-up
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* immediately after link-up
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@@ -894,6 +919,34 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
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return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
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return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
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}
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}
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+/**
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+ * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
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+ * @hw: pointer to the HW structure
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+ *
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+ * Assumes semaphore already acquired.
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+ *
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+ **/
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+static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
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+{
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+ u16 phy_data;
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+ u32 strap = er32(STRAP);
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+ s32 ret_val = 0;
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+
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+ strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
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+
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+ ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
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+ if (ret_val)
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+ goto out;
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+
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+ phy_data &= ~HV_SMB_ADDR_MASK;
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+ phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
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+ phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
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+ ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
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+
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+out:
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+ return ret_val;
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+}
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+
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/**
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/**
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* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
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* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
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* @hw: pointer to the HW structure
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* @hw: pointer to the HW structure
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@@ -903,7 +956,6 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
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**/
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**/
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static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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{
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{
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- struct e1000_adapter *adapter = hw->adapter;
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struct e1000_phy_info *phy = &hw->phy;
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
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u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
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s32 ret_val = 0;
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s32 ret_val = 0;
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@@ -921,7 +973,8 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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if (phy->type != e1000_phy_igp_3)
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if (phy->type != e1000_phy_igp_3)
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return ret_val;
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return ret_val;
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- if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
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+ if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
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+ (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
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sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
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sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
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break;
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break;
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}
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}
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@@ -961,21 +1014,16 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
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cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
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cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
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cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
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- if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
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- ((hw->mac.type == e1000_pchlan) ||
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- (hw->mac.type == e1000_pch2lan))) {
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+ if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
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+ (hw->mac.type == e1000_pchlan)) ||
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+ (hw->mac.type == e1000_pch2lan)) {
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/*
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/*
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* HW configures the SMBus address and LEDs when the
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* HW configures the SMBus address and LEDs when the
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* OEM and LCD Write Enable bits are set in the NVM.
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* OEM and LCD Write Enable bits are set in the NVM.
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* When both NVM bits are cleared, SW will configure
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* When both NVM bits are cleared, SW will configure
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* them instead.
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* them instead.
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*/
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*/
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- data = er32(STRAP);
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- data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
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- reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
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- reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
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- ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
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- reg_data);
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+ ret_val = e1000_write_smbus_addr(hw);
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if (ret_val)
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if (ret_val)
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goto out;
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goto out;
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@@ -1440,10 +1488,6 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
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goto out;
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goto out;
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/* Enable jumbo frame workaround in the PHY */
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/* Enable jumbo frame workaround in the PHY */
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- e1e_rphy(hw, PHY_REG(769, 20), &data);
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- ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
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- if (ret_val)
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- goto out;
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e1e_rphy(hw, PHY_REG(769, 23), &data);
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e1e_rphy(hw, PHY_REG(769, 23), &data);
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data &= ~(0x7F << 5);
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data &= ~(0x7F << 5);
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data |= (0x37 << 5);
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data |= (0x37 << 5);
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@@ -1452,7 +1496,6 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
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goto out;
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goto out;
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e1e_rphy(hw, PHY_REG(769, 16), &data);
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e1e_rphy(hw, PHY_REG(769, 16), &data);
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data &= ~(1 << 13);
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data &= ~(1 << 13);
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- data |= (1 << 12);
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ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
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ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
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if (ret_val)
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if (ret_val)
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goto out;
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goto out;
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@@ -1477,7 +1520,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
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mac_reg = er32(RCTL);
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mac_reg = er32(RCTL);
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mac_reg &= ~E1000_RCTL_SECRC;
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mac_reg &= ~E1000_RCTL_SECRC;
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- ew32(FFLT_DBG, mac_reg);
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+ ew32(RCTL, mac_reg);
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ret_val = e1000e_read_kmrn_reg(hw,
|
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ret_val = e1000e_read_kmrn_reg(hw,
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E1000_KMRNCTRLSTA_CTRL_OFFSET,
|
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E1000_KMRNCTRLSTA_CTRL_OFFSET,
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@@ -1503,17 +1546,12 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
|
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goto out;
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goto out;
|
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|
|
|
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/* Write PHY register values back to h/w defaults */
|
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/* Write PHY register values back to h/w defaults */
|
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- e1e_rphy(hw, PHY_REG(769, 20), &data);
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|
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- ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
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|
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- if (ret_val)
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- goto out;
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e1e_rphy(hw, PHY_REG(769, 23), &data);
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e1e_rphy(hw, PHY_REG(769, 23), &data);
|
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data &= ~(0x7F << 5);
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data &= ~(0x7F << 5);
|
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ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
|
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ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
|
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if (ret_val)
|
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if (ret_val)
|
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goto out;
|
|
goto out;
|
|
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
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e1e_rphy(hw, PHY_REG(769, 16), &data);
|
|
- data &= ~(1 << 12);
|
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|
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data |= (1 << 13);
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data |= (1 << 13);
|
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ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
|
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
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if (ret_val)
|
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if (ret_val)
|
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@@ -1558,6 +1596,69 @@ out:
|
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return ret_val;
|
|
return ret_val;
|
|
}
|
|
}
|
|
|
|
|
|
|
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+/**
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|
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+ * e1000_k1_gig_workaround_lv - K1 Si workaround
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|
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+ * @hw: pointer to the HW structure
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|
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+ *
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|
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+ * Workaround to set the K1 beacon duration for 82579 parts
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|
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+ **/
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|
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+static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
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|
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+{
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|
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+ s32 ret_val = 0;
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|
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+ u16 status_reg = 0;
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|
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+ u32 mac_reg;
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|
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+
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|
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+ if (hw->mac.type != e1000_pch2lan)
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|
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+ goto out;
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|
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+
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|
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+ /* Set K1 beacon duration based on 1Gbps speed or otherwise */
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|
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+ ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
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|
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+ if (ret_val)
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|
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+ goto out;
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|
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+
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|
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+ if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
|
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|
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+ == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
|
|
|
|
+ mac_reg = er32(FEXTNVM4);
|
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|
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+ mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
|
|
|
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+
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|
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+ if (status_reg & HV_M_STATUS_SPEED_1000)
|
|
|
|
+ mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
|
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|
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+ else
|
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|
|
+ mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
|
|
|
|
+
|
|
|
|
+ ew32(FEXTNVM4, mac_reg);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+out:
|
|
|
|
+ return ret_val;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/**
|
|
|
|
+ * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
|
|
|
|
+ * @hw: pointer to the HW structure
|
|
|
|
+ * @gate: boolean set to true to gate, false to ungate
|
|
|
|
+ *
|
|
|
|
+ * Gate/ungate the automatic PHY configuration via hardware; perform
|
|
|
|
+ * the configuration via software instead.
|
|
|
|
+ **/
|
|
|
|
+static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
|
|
|
|
+{
|
|
|
|
+ u32 extcnf_ctrl;
|
|
|
|
+
|
|
|
|
+ if (hw->mac.type != e1000_pch2lan)
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ extcnf_ctrl = er32(EXTCNF_CTRL);
|
|
|
|
+
|
|
|
|
+ if (gate)
|
|
|
|
+ extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
|
|
|
|
+ else
|
|
|
|
+ extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
|
|
|
|
+
|
|
|
|
+ ew32(EXTCNF_CTRL, extcnf_ctrl);
|
|
|
|
+ return;
|
|
|
|
+}
|
|
|
|
+
|
|
/**
|
|
/**
|
|
* e1000_lan_init_done_ich8lan - Check for PHY config completion
|
|
* e1000_lan_init_done_ich8lan - Check for PHY config completion
|
|
* @hw: pointer to the HW structure
|
|
* @hw: pointer to the HW structure
|
|
@@ -1602,6 +1703,9 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
|
|
if (e1000_check_reset_block(hw))
|
|
if (e1000_check_reset_block(hw))
|
|
goto out;
|
|
goto out;
|
|
|
|
|
|
|
|
+ /* Allow time for h/w to get to quiescent state after reset */
|
|
|
|
+ msleep(10);
|
|
|
|
+
|
|
/* Perform any necessary post-reset workarounds */
|
|
/* Perform any necessary post-reset workarounds */
|
|
switch (hw->mac.type) {
|
|
switch (hw->mac.type) {
|
|
case e1000_pchlan:
|
|
case e1000_pchlan:
|
|
@@ -1630,6 +1734,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
|
|
/* Configure the LCD with the OEM bits in NVM */
|
|
/* Configure the LCD with the OEM bits in NVM */
|
|
ret_val = e1000_oem_bits_config_ich8lan(hw, true);
|
|
ret_val = e1000_oem_bits_config_ich8lan(hw, true);
|
|
|
|
|
|
|
|
+ /* Ungate automatic PHY configuration on non-managed 82579 */
|
|
|
|
+ if ((hw->mac.type == e1000_pch2lan) &&
|
|
|
|
+ !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
|
|
|
|
+ msleep(10);
|
|
|
|
+ e1000_gate_hw_phy_config_ich8lan(hw, false);
|
|
|
|
+ }
|
|
|
|
+
|
|
out:
|
|
out:
|
|
return ret_val;
|
|
return ret_val;
|
|
}
|
|
}
|
|
@@ -1646,6 +1757,11 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
|
|
{
|
|
{
|
|
s32 ret_val = 0;
|
|
s32 ret_val = 0;
|
|
|
|
|
|
|
|
+ /* Gate automatic PHY configuration by hardware on non-managed 82579 */
|
|
|
|
+ if ((hw->mac.type == e1000_pch2lan) &&
|
|
|
|
+ !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
|
|
|
|
+ e1000_gate_hw_phy_config_ich8lan(hw, true);
|
|
|
|
+
|
|
ret_val = e1000e_phy_hw_reset_generic(hw);
|
|
ret_val = e1000e_phy_hw_reset_generic(hw);
|
|
if (ret_val)
|
|
if (ret_val)
|
|
goto out;
|
|
goto out;
|
|
@@ -2910,6 +3026,14 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
|
|
* external PHY is reset.
|
|
* external PHY is reset.
|
|
*/
|
|
*/
|
|
ctrl |= E1000_CTRL_PHY_RST;
|
|
ctrl |= E1000_CTRL_PHY_RST;
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * Gate automatic PHY configuration by hardware on
|
|
|
|
+ * non-managed 82579
|
|
|
|
+ */
|
|
|
|
+ if ((hw->mac.type == e1000_pch2lan) &&
|
|
|
|
+ !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
|
|
|
|
+ e1000_gate_hw_phy_config_ich8lan(hw, true);
|
|
}
|
|
}
|
|
ret_val = e1000_acquire_swflag_ich8lan(hw);
|
|
ret_val = e1000_acquire_swflag_ich8lan(hw);
|
|
e_dbg("Issuing a global reset to ich8lan\n");
|
|
e_dbg("Issuing a global reset to ich8lan\n");
|
|
@@ -3460,13 +3584,20 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
|
|
void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
|
|
void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
|
|
{
|
|
{
|
|
u32 phy_ctrl;
|
|
u32 phy_ctrl;
|
|
|
|
+ s32 ret_val;
|
|
|
|
|
|
phy_ctrl = er32(PHY_CTRL);
|
|
phy_ctrl = er32(PHY_CTRL);
|
|
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
|
|
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
|
|
ew32(PHY_CTRL, phy_ctrl);
|
|
ew32(PHY_CTRL, phy_ctrl);
|
|
|
|
|
|
- if (hw->mac.type >= e1000_pchlan)
|
|
|
|
- e1000_phy_hw_reset_ich8lan(hw);
|
|
|
|
|
|
+ if (hw->mac.type >= e1000_pchlan) {
|
|
|
|
+ e1000_oem_bits_config_ich8lan(hw, true);
|
|
|
|
+ ret_val = hw->phy.ops.acquire(hw);
|
|
|
|
+ if (ret_val)
|
|
|
|
+ return;
|
|
|
|
+ e1000_write_smbus_addr(hw);
|
|
|
|
+ hw->phy.ops.release(hw);
|
|
|
|
+ }
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
/**
|