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@@ -1665,6 +1665,40 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
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rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
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+ rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
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+ if (rt2x00_rt(rt2x00dev, RT3390)) {
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
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+ rt2x00dev->default_ant.rx_chain_num == 1);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
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+ rt2x00dev->default_ant.tx_chain_num == 1);
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+ } else {
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
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+
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+ switch (rt2x00dev->default_ant.tx_chain_num) {
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+ case 1:
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
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+ /* fall through */
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+ case 2:
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
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+ break;
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+ }
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+
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+ switch (rt2x00dev->default_ant.rx_chain_num) {
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+ case 1:
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
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+ /* fall through */
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+ case 2:
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
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+ break;
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+ }
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+ }
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+ rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
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+
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rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
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rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
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