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@@ -33,8 +33,8 @@ static int debug;
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if (debug) printk (KERN_DEBUG "cx24123: " args); \
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} while (0)
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-struct cx24123_state {
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-
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+struct cx24123_state
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+{
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struct i2c_adapter* i2c;
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struct dvb_frontend_ops ops;
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const struct cx24123_config* config;
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@@ -56,6 +56,148 @@ struct cx24123_state {
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u32 currentsymbolrate;
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};
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+/* Various tuner defaults need to be established for a given symbol rate Sps */
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+static struct
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+{
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+ u32 symbolrate_low;
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+ u32 symbolrate_high;
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+ u32 VCAslope;
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+ u32 VCAoffset;
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+ u32 VGA1offset;
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+ u32 VGA2offset;
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+ u32 VCAprogdata;
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+ u32 VGAprogdata;
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+} cx24123_AGC_vals[] =
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+{
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+ {
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+ .symbolrate_low = 1000000,
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+ .symbolrate_high = 4999999,
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+ .VCAslope = 0x07,
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+ .VCAoffset = 0x0f,
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+ .VGA1offset = 0x1f8,
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+ .VGA2offset = 0x1f8,
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+ .VGAprogdata = (2 << 18) | (0x1f8 << 9) | 0x1f8,
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+ .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x07,
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+ },
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+ {
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+ .symbolrate_low = 5000000,
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+ .symbolrate_high = 14999999,
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+ .VCAslope = 0x1f,
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+ .VCAoffset = 0x1f,
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+ .VGA1offset = 0x1e0,
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+ .VGA2offset = 0x180,
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+ .VGAprogdata = (2 << 18) | (0x180 << 9) | 0x1e0,
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+ .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x1f,
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+ },
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+ {
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+ .symbolrate_low = 15000000,
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+ .symbolrate_high = 45000000,
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+ .VCAslope = 0x3f,
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+ .VCAoffset = 0x3f,
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+ .VGA1offset = 0x180,
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+ .VGA2offset = 0x100,
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+ .VGAprogdata = (2 << 18) | (0x100 << 9) | 0x180,
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+ .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x3f,
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+ },
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+};
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+
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+/*
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+ * Various tuner defaults need to be established for a given frequency kHz.
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+ * fixme: The bounds on the bands do not match the doc in real life.
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+ * fixme: Some of them have been moved, other might need adjustment.
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+ */
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+static struct
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+{
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+ u32 freq_low;
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+ u32 freq_high;
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+ u32 bandselect;
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+ u32 VCOdivider;
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+ u32 VCOnumber;
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+ u32 progdata;
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+} cx24123_bandselect_vals[] =
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+{
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+ {
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+ .freq_low = 950000,
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+ .freq_high = 1018999,
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+ .bandselect = 0x40,
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+ .VCOdivider = 4,
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+ .VCOnumber = 7,
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+ .progdata = (0 << 18) | (0 << 9) | 0x40,
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+ },
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+ {
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+ .freq_low = 1019000,
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+ .freq_high = 1074999,
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+ .bandselect = 0x80,
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+ .VCOdivider = 4,
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+ .VCOnumber = 8,
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+ .progdata = (0 << 18) | (0 << 9) | 0x80,
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+ },
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+ {
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+ .freq_low = 1075000,
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+ .freq_high = 1227999,
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+ .bandselect = 0x01,
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+ .VCOdivider = 2,
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+ .VCOnumber = 1,
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+ .progdata = (0 << 18) | (1 << 9) | 0x01,
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+ },
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+ {
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+ .freq_low = 1228000,
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+ .freq_high = 1349999,
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+ .bandselect = 0x02,
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+ .VCOdivider = 2,
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+ .VCOnumber = 2,
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+ .progdata = (0 << 18) | (1 << 9) | 0x02,
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+ },
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+ {
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+ .freq_low = 1350000,
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+ .freq_high = 1481999,
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+ .bandselect = 0x04,
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+ .VCOdivider = 2,
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+ .VCOnumber = 3,
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+ .progdata = (0 << 18) | (1 << 9) | 0x04,
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+ },
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+ {
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+ .freq_low = 1482000,
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+ .freq_high = 1595999,
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+ .bandselect = 0x08,
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+ .VCOdivider = 2,
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+ .VCOnumber = 4,
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+ .progdata = (0 << 18) | (1 << 9) | 0x08,
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+ },
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+ {
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+ .freq_low = 1596000,
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+ .freq_high = 1717999,
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+ .bandselect = 0x10,
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+ .VCOdivider = 2,
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+ .VCOnumber = 5,
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+ .progdata = (0 << 18) | (1 << 9) | 0x10,
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+ },
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+ {
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+ .freq_low = 1718000,
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+ .freq_high = 1855999,
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+ .bandselect = 0x20,
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+ .VCOdivider = 2,
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+ .VCOnumber = 6,
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+ .progdata = (0 << 18) | (1 << 9) | 0x20,
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+ },
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+ {
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+ .freq_low = 1856000,
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+ .freq_high = 2035999,
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+ .bandselect = 0x40,
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+ .VCOdivider = 2,
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+ .VCOnumber = 7,
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+ .progdata = (0 << 18) | (1 << 9) | 0x40,
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+ },
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+ {
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+ .freq_low = 2036000,
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+ .freq_high = 2149999,
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+ .bandselect = 0x80,
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+ .VCOdivider = 2,
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+ .VCOnumber = 8,
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+ .progdata = (0 << 18) | (1 << 9) | 0x80,
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+ },
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+};
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+
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static struct {
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u8 reg;
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u8 data;
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@@ -195,9 +337,9 @@ static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_invers
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val = cx24123_readreg(state, 0x1b) >> 7;
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if (val == 0)
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- *inversion=INVERSION_OFF;
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+ *inversion = INVERSION_OFF;
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else
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- *inversion=INVERSION_ON;
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+ *inversion = INVERSION_ON;
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return 0;
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}
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@@ -205,12 +347,12 @@ static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_invers
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static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
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{
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if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
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- fec=FEC_AUTO;
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+ fec = FEC_AUTO;
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/* Hardware has 5/11 and 3/5 but are never unused */
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switch (fec) {
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case FEC_NONE:
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- return cx24123_writereg(state, 0x0f,0x01);
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+ return cx24123_writereg(state, 0x0f, 0x01);
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case FEC_1_2:
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return cx24123_writereg(state, 0x0f, 0x02);
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case FEC_2_3:
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@@ -230,37 +372,41 @@ static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
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static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
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{
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+ int ret;
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u8 val;
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- val = cx24123_readreg (state, 0x1b) & 0x07;
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+ ret = cx24123_readreg (state, 0x1b);
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+ if (ret < 0)
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+ return ret;
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+ val = ret & 0x07;
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switch (val) {
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case 1:
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- *fec=FEC_1_2;
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- return 0;
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+ *fec = FEC_1_2;
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+ break;
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case 3:
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- *fec=FEC_2_3;
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- return 0;
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+ *fec = FEC_2_3;
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+ break;
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case 4:
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- *fec=FEC_3_4;
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- return 0;
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+ *fec = FEC_3_4;
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+ break;
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case 5:
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- *fec=FEC_4_5;
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- return 0;
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+ *fec = FEC_4_5;
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+ break;
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case 6:
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- *fec=FEC_5_6;
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- return 0;
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+ *fec = FEC_5_6;
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+ break;
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case 7:
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- *fec=FEC_7_8;
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- return 0;
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- case 2: /* *fec=FEC_3_5; return 0; */
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- case 0: /* *fec=FEC_5_11; return 0; */
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- *fec=FEC_AUTO;
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- return 0;
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+ *fec = FEC_7_8;
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+ break;
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+ case 2: /* *fec = FEC_3_5; break; */
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+ case 0: /* *fec = FEC_5_11; break; */
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+ *fec = FEC_AUTO;
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+ break;
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default:
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- *fec=FEC_NONE; return 0;
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+ *fec = FEC_NONE; // can't happen
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}
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- return -EREMOTEIO;
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+ return 0;
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}
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/* fixme: Symbol rates < 3MSps may not work because of precision loss */
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@@ -268,14 +414,14 @@ static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
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{
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u32 val;
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- val = (srate/1185)*100;
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+ val = (srate / 1185) * 100;
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/* Compensate for scaling up, by removing 17 symbols per 1Msps */
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- val = val - (17*(srate / 1000000));
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+ val = val - (17 * (srate / 1000000));
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- cx24123_writereg(state, 0x08, (val >>16) & 0xff );
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- cx24123_writereg(state, 0x09, (val >> 8) & 0xff );
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- cx24123_writereg(state, 0x0a, (val ) & 0xff );
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+ cx24123_writereg(state, 0x08, (val >> 16) & 0xff );
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+ cx24123_writereg(state, 0x09, (val >> 8) & 0xff );
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+ cx24123_writereg(state, 0x0a, (val ) & 0xff );
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return 0;
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}
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@@ -287,8 +433,8 @@ static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
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static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
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{
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struct cx24123_state *state = fe->demodulator_priv;
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- u32 ndiv=0, adiv=0, vco_div=0;
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- int i=0;
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+ u32 ndiv = 0, adiv = 0, vco_div = 0;
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+ int i = 0;
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/* Defaults for low freq, low rate */
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state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
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@@ -297,7 +443,7 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
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vco_div = cx24123_bandselect_vals[0].VCOdivider;
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/* For the given symbolerate, determine the VCA and VGA programming bits */
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- for (i=0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
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+ for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
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{
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if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
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(cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
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@@ -307,7 +453,7 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
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}
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/* For the given frequency, determine the bandselect programming bits */
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- for (i=0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
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+ for (i = 0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
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{
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if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
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(cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
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@@ -340,7 +486,7 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
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{
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struct cx24123_state *state = fe->demodulator_priv;
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- u8 timeout=0;
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+ u8 timeout = 0;
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/* align the 21 bytes into to bit23 boundary */
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data = data << 3;
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@@ -348,9 +494,9 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
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/* Reset the demod pll word length to 0x15 bits */
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cx24123_writereg(state, 0x21, 0x15);
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- timeout=0;
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+ timeout = 0;
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/* write the msb 8 bits, wait for the send to be completed */
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- cx24123_writereg(state, 0x22, (data>>16) & 0xff);
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+ cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
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while ( ( cx24123_readreg(state, 0x20) & 0x40 ) == 0 )
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{
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/* Safety - No reason why the write should not complete, and we never get here, avoid hang */
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@@ -361,7 +507,7 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
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msleep(500);
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}
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- timeout=0;
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+ timeout = 0;
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/* send another 8 bytes, wait for the send to be completed */
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cx24123_writereg(state, 0x22, (data>>8) & 0xff );
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while ( (cx24123_readreg(state, 0x20) & 0x40 ) == 0 )
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@@ -374,7 +520,7 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
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msleep(500);
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}
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- timeout=0;
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+ timeout = 0;
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/* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
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cx24123_writereg(state, 0x22, (data) & 0xff );
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while ((cx24123_readreg(state, 0x20) & 0x80))
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@@ -398,7 +544,7 @@ static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_paramet
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{
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struct cx24123_state *state = fe->demodulator_priv;
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- if (cx24123_pll_calculate(fe, p)!=0) {
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+ if (cx24123_pll_calculate(fe, p) != 0) {
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printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
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return -EINVAL;
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}
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@@ -420,7 +566,7 @@ static int cx24123_initfe(struct dvb_frontend* fe)
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int i;
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/* Configure the demod to a good set of defaults */
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- for (i=0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
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+ for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
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cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
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if (state->config->pll_init)
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@@ -452,7 +598,7 @@ static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage
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}
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static int cx24123_send_diseqc_msg(struct dvb_frontend* fe,
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- struct dvb_diseqc_master_cmd *cmd)
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+ struct dvb_diseqc_master_cmd *cmd)
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{
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/* fixme: Implement diseqc */
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printk("%s: No support yet\n",__FUNCTION__);
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@@ -545,7 +691,7 @@ static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
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state->config->set_ts_params(fe, 0);
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state->currentfreq=p->frequency;
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- state->currentsymbolrate=p->u.qpsk.symbol_rate;
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+ state->currentsymbolrate = p->u.qpsk.symbol_rate;
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cx24123_set_inversion(state, p->inversion);
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cx24123_set_fec(state, p->u.qpsk.fec_inner);
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@@ -553,7 +699,7 @@ static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
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cx24123_pll_tune(fe, p);
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/* Enable automatic aquisition and reset cycle */
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- cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07) );
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+ cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
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cx24123_writereg(state, 0x00, 0x10);
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cx24123_writereg(state, 0x00, 0);
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@@ -605,7 +751,8 @@ static void cx24123_release(struct dvb_frontend* fe)
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static struct dvb_frontend_ops cx24123_ops;
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-struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, struct i2c_adapter* i2c)
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+struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
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+ struct i2c_adapter* i2c)
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{
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struct cx24123_state* state = NULL;
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int ret;
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@@ -691,4 +838,3 @@ MODULE_AUTHOR("Steven Toth");
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MODULE_LICENSE("GPL");
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EXPORT_SYMBOL(cx24123_attach);
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-
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