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@@ -106,3 +106,51 @@ u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
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}
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+
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+#ifdef CONFIG_BCMA_DRIVER_MIPS
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+void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
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+{
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+ unsigned int irq;
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+ u32 baud_base;
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+ u32 i;
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+ unsigned int ccrev = cc->core->id.rev;
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+ struct bcma_serial_port *ports = cc->serial_ports;
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+
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+ if (ccrev >= 11 && ccrev != 15) {
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+ /* Fixed ALP clock */
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+ baud_base = bcma_pmu_alp_clock(cc);
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+ if (ccrev >= 21) {
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+ /* Turn off UART clock before switching clocksource. */
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+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
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+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
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+ & ~BCMA_CC_CORECTL_UARTCLKEN);
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+ }
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+ /* Set the override bit so we don't divide it */
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+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
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+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
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+ | BCMA_CC_CORECTL_UARTCLK0);
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+ if (ccrev >= 21) {
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+ /* Re-enable the UART clock. */
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+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
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+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
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+ | BCMA_CC_CORECTL_UARTCLKEN);
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+ }
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+ } else {
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+ pr_err("serial not supported on this device ccrev: 0x%x\n",
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+ ccrev);
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+ return;
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+ }
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+
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+ irq = bcma_core_mips_irq(cc->core);
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+
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+ /* Determine the registers of the UARTs */
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+ cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
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+ for (i = 0; i < cc->nr_serial_ports; i++) {
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+ ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
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+ (i * 256);
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+ ports[i].irq = irq;
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+ ports[i].baud_base = baud_base;
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+ ports[i].reg_shift = 0;
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+ }
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+}
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+#endif /* CONFIG_BCMA_DRIVER_MIPS */
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