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@@ -1,7 +1,7 @@
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/*
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/*
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* linux/arch/arm/mach-pxa/irq.c
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* linux/arch/arm/mach-pxa/irq.c
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*
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*
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- * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
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+ * Generic PXA IRQ handling
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*
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*
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* Author: Nicolas Pitre
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Created: Jun 15, 2001
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@@ -104,188 +104,6 @@ void __init pxa_init_irq_high(void)
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}
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}
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#endif
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#endif
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-/*
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- * PXA GPIO edge detection for IRQs:
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- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
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- * Use this instead of directly setting GRER/GFER.
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- */
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-
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-static long GPIO_IRQ_rising_edge[4];
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-static long GPIO_IRQ_falling_edge[4];
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-static long GPIO_IRQ_mask[4];
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-
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-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
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-{
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- int gpio, idx;
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-
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- gpio = IRQ_TO_GPIO(irq);
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- idx = gpio >> 5;
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-
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- if (type == IRQ_TYPE_PROBE) {
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- /* Don't mess with enabled GPIOs using preconfigured edges or
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- * GPIOs set to alternate function or to output during probe
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- */
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- if ((GPIO_IRQ_rising_edge[idx] |
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- GPIO_IRQ_falling_edge[idx] |
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- GPDR(gpio)) & GPIO_bit(gpio))
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- return 0;
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- if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
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- return 0;
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- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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- }
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-
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- pxa_gpio_mode(gpio | GPIO_IN);
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-
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- if (type & IRQ_TYPE_EDGE_RISING)
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- __set_bit(gpio, GPIO_IRQ_rising_edge);
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- else
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- __clear_bit(gpio, GPIO_IRQ_rising_edge);
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-
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- if (type & IRQ_TYPE_EDGE_FALLING)
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- __set_bit(gpio, GPIO_IRQ_falling_edge);
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- else
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- __clear_bit(gpio, GPIO_IRQ_falling_edge);
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-
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- GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
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- GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
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-
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- pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
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- ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
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- ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
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- return 0;
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-}
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-
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-/*
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- * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
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- */
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-
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-static void pxa_ack_low_gpio(unsigned int irq)
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-{
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- GEDR0 = (1 << (irq - IRQ_GPIO0));
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-}
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-
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-static void pxa_mask_low_gpio(unsigned int irq)
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-{
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- ICMR &= ~(1 << (irq - PXA_IRQ(0)));
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-}
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-
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-static void pxa_unmask_low_gpio(unsigned int irq)
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-{
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- ICMR |= 1 << (irq - PXA_IRQ(0));
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-}
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-
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-static struct irq_chip pxa_low_gpio_chip = {
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- .name = "GPIO-l",
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- .ack = pxa_ack_low_gpio,
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- .mask = pxa_mask_low_gpio,
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- .unmask = pxa_unmask_low_gpio,
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- .set_type = pxa_gpio_irq_type,
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-};
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-
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-/*
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- * Demux handler for GPIO>=2 edge detect interrupts
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- */
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-
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-#define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
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-
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-static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
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-{
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- int loop, bit, n;
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- unsigned long gedr[4];
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-
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- do {
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- gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
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- gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
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- gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
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- gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
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-
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- GEDR0 = gedr[0]; GEDR1 = gedr[1];
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- GEDR2 = gedr[2]; GEDR3 = gedr[3];
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-
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- loop = 0;
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- bit = find_first_bit(gedr, GEDR_BITS);
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- while (bit < GEDR_BITS) {
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- loop = 1;
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-
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- n = PXA_GPIO_IRQ_BASE + bit;
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- desc_handle_irq(n, irq_desc + n);
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-
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- bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
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- }
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- } while (loop);
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-}
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-
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-static void pxa_ack_muxed_gpio(unsigned int irq)
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-{
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- int gpio = irq - IRQ_GPIO(2) + 2;
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- GEDR(gpio) = GPIO_bit(gpio);
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-}
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-
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-static void pxa_mask_muxed_gpio(unsigned int irq)
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-{
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- int gpio = irq - IRQ_GPIO(2) + 2;
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- __clear_bit(gpio, GPIO_IRQ_mask);
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- GRER(gpio) &= ~GPIO_bit(gpio);
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- GFER(gpio) &= ~GPIO_bit(gpio);
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-}
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-
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-static void pxa_unmask_muxed_gpio(unsigned int irq)
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-{
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- int gpio = irq - IRQ_GPIO(2) + 2;
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- int idx = gpio >> 5;
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- __set_bit(gpio, GPIO_IRQ_mask);
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- GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
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- GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
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-}
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-
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-static struct irq_chip pxa_muxed_gpio_chip = {
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- .name = "GPIO",
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- .ack = pxa_ack_muxed_gpio,
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- .mask = pxa_mask_muxed_gpio,
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- .unmask = pxa_unmask_muxed_gpio,
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- .set_type = pxa_gpio_irq_type,
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-};
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-
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-void __init pxa_init_irq_gpio(int gpio_nr)
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-{
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- int irq, i;
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-
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- pxa_last_gpio = gpio_nr - 1;
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-
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- /* clear all GPIO edge detects */
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- for (i = 0; i < gpio_nr; i += 32) {
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- GFER(i) = 0;
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- GRER(i) = 0;
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- GEDR(i) = GEDR(i);
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- }
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-
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- /* GPIO 0 and 1 must have their mask bit always set */
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- GPIO_IRQ_mask[0] = 3;
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-
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- for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
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- set_irq_chip(irq, &pxa_low_gpio_chip);
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- set_irq_handler(irq, handle_edge_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- }
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-
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- for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
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- set_irq_chip(irq, &pxa_muxed_gpio_chip);
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- set_irq_handler(irq, handle_edge_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- }
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-
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- /* Install handler for GPIO>=2 edge detect interrupts */
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- set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
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-
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- pxa_init_gpio(gpio_nr);
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-}
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-
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-void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int))
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-{
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- pxa_low_gpio_chip.set_wake = set_wake;
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- pxa_muxed_gpio_chip.set_wake = set_wake;
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-}
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-
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void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
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void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
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{
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{
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pxa_internal_chip_low.set_wake = set_wake;
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pxa_internal_chip_low.set_wake = set_wake;
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