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@@ -55,7 +55,7 @@ static void quirk_mellanox_tavor(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
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-/* Deal with broken BIOS'es that neglect to enable passive release,
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+/* Deal with broken BIOSes that neglect to enable passive release,
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which can cause problems in combination with the 82441FX/PPro MTRRs */
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static void quirk_passive_release(struct pci_dev *dev)
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{
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@@ -78,11 +78,11 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_p
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/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
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but VIA don't answer queries. If you happen to have good contacts at VIA
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- ask them for me please -- Alan
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-
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- This appears to be BIOS not version dependent. So presumably there is a
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+ ask them for me please -- Alan
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+
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+ This appears to be BIOS not version dependent. So presumably there is a
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chipset level fix */
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-
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+
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static void quirk_isa_dma_hangs(struct pci_dev *dev)
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{
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if (!isa_dma_bridge_buggy) {
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@@ -97,7 +97,7 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
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@@ -157,10 +157,10 @@ static void quirk_triton(struct pci_dev *dev)
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pci_pci_problems |= PCIPCI_TRITON;
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}
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}
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
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/*
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* VIA Apollo KT133 needs PCI latency patch
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@@ -171,7 +171,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quir
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* the info on which Mr Breese based his work.
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*
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* Updated based on further information from the site and also on
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- * information provided by VIA
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+ * information provided by VIA
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*/
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static void quirk_vialatency(struct pci_dev *dev)
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{
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@@ -179,7 +179,7 @@ static void quirk_vialatency(struct pci_dev *dev)
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u8 busarb;
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/* Ok we have a potential problem chipset here. Now see if we have
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a buggy southbridge */
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-
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+
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p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
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if (p!=NULL) {
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/* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
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@@ -194,9 +194,9 @@ static void quirk_vialatency(struct pci_dev *dev)
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if (p->revision < 0x10 || p->revision > 0x12)
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goto exit;
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}
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-
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+
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/*
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- * Ok we have the problem. Now set the PCI master grant to
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+ * Ok we have the problem. Now set the PCI master grant to
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* occur every master grant. The apparent bug is that under high
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* PCI load (quite common in Linux of course) you can get data
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* loss when the CPU is held off the bus for 3 bus master requests
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@@ -209,7 +209,7 @@ static void quirk_vialatency(struct pci_dev *dev)
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*/
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pci_read_config_byte(dev, 0x76, &busarb);
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- /* Set bit 4 and bi 5 of byte 76 to 0x01
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+ /* Set bit 4 and bi 5 of byte 76 to 0x01
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"Master priority rotation on every PCI master grant */
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busarb &= ~(1<<5);
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busarb |= (1<<4);
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@@ -252,7 +252,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx)
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* that DMA to AGP space. Latency must be set to 0xA and triton
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* workaround applied too
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* [Info kindly provided by ALi]
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- */
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+ */
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static void quirk_alimagik(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
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@@ -260,8 +260,8 @@ static void quirk_alimagik(struct pci_dev *dev)
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pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
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}
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}
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
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/*
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* Natoma has some interesting boundary conditions with Zoran stuff
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@@ -274,12 +274,12 @@ static void quirk_natoma(struct pci_dev *dev)
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pci_pci_problems |= PCIPCI_NATOMA;
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}
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}
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
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/*
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* This chip can cause PCI parity errors if config register 0xA0 is read
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@@ -400,7 +400,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
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/*
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* For now we only print it out. Eventually we'll want to
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* reserve it (at least if it's in the 0x1000+ range), but
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- * let's get enough confirmation reports first.
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+ * let's get enough confirmation reports first.
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*/
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base &= -size;
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dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
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@@ -425,7 +425,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
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}
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/*
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* For now we only print it out. Eventually we'll want to
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- * reserve it, but let's get enough confirmation reports first.
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+ * reserve it, but let's get enough confirmation reports first.
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*/
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base &= -size;
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dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
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@@ -682,7 +682,7 @@ static void quirk_xio2000a(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
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quirk_xio2000a);
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-#ifdef CONFIG_X86_IO_APIC
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+#ifdef CONFIG_X86_IO_APIC
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#include <asm/io_apic.h>
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@@ -696,12 +696,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
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static void quirk_via_ioapic(struct pci_dev *dev)
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{
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u8 tmp;
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-
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+
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if (nr_ioapics < 1)
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tmp = 0; /* nothing routed to external APIC */
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else
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tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
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-
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+
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dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
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tmp == 0 ? "Disa" : "Ena");
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@@ -712,7 +712,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_i
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DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
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/*
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- * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
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+ * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
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* This leads to doubled level interrupt rates.
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* Set this bit to get rid of cycle wastage.
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* Otherwise uncritical.
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@@ -986,7 +986,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, qu
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static void quirk_disable_pxb(struct pci_dev *pdev)
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{
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u16 config;
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-
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+
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if (pdev->revision != 0x04) /* Only C0 requires this */
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return;
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pci_read_config_word(pdev, 0x40, &config);
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@@ -1094,11 +1094,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_e
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* On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
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* is not activated. The myth is that Asus said that they do not want the
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* users to be irritated by just another PCI Device in the Win98 device
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- * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
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+ * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
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* package 2.7.0 for details)
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*
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- * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
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- * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
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+ * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
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+ * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
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* becomes necessary to do this tweak in two steps -- the chosen trigger
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* is either the Host bridge (preferred) or on-board VGA controller.
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*
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@@ -1253,7 +1253,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asu
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static void asus_hides_smbus_lpc(struct pci_dev *dev)
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{
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u16 val;
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-
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+
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if (likely(!asus_hides_smbus))
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return;
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@@ -1640,8 +1640,8 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
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dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
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dev->vendor, dev->device);
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}
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
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-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
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+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
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/*
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* disable boot interrupts on HT-1000
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@@ -1673,8 +1673,8 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
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dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
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dev->vendor, dev->device);
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}
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
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-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
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+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
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/*
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* disable boot interrupts on AMD and ATI chipsets
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@@ -1730,8 +1730,8 @@ static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
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dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
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dev->vendor, dev->device);
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}
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-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
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-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
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+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
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#endif /* CONFIG_X86_IO_APIC */
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/*
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@@ -2127,8 +2127,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
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#ifdef CONFIG_PCI_MSI
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/* Some chipsets do not support MSI. We cannot easily rely on setting
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* PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
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- * some other busses controlled by the chipset even if Linux is not
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- * aware of it. Instead of setting the flag on all busses in the
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+ * some other buses controlled by the chipset even if Linux is not
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+ * aware of it. Instead of setting the flag on all buses in the
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* machine, simply disable MSI globally.
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*/
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static void quirk_disable_all_msi(struct pci_dev *dev)
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@@ -2288,14 +2288,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
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nvenet_msi_disable);
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/*
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- * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
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- * config register. This register controls the routing of legacy interrupts
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- * from devices that route through the MCP55. If this register is misprogramed
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- * interrupts are only sent to the bsp, unlike conventional systems where the
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- * irq is broadxast to all online cpus. Not having this register set
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- * properly prevents kdump from booting up properly, so lets make sure that
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- * we have it set correctly.
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- * Note this is an undocumented register.
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+ * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
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+ * config register. This register controls the routing of legacy
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+ * interrupts from devices that route through the MCP55. If this register
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+ * is misprogrammed, interrupts are only sent to the BSP, unlike
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+ * conventional systems where the IRQ is broadcast to all online CPUs. Not
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+ * having this register set properly prevents kdump from booting up
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+ * properly, so let's make sure that we have it set correctly.
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+ * Note that this is an undocumented register.
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*/
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static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
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{
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@@ -2626,7 +2626,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
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/* Allow manual resource allocation for PCI hotplug bridges
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* via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
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* some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
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- * kernel fails to allocate resources when hotplug device is
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+ * kernel fails to allocate resources when hotplug device is
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* inserted and PCI bus is rescanned.
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*/
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static void quirk_hotplug_bridge(struct pci_dev *dev)
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